Context Navigation

Register_Address_Translation_unit_function_one_save_transition.cpp @ 145

Last change on this file since 145 was 145, checked in by rosiere, 14 years ago
1) add test with SPECINT2K 2) new config of Selftest 3) modif RAT to support multiple depth_save ... but not finish (need fix Update Prediction Table) 4) add Function_pointer but need fix
Property svn:keywords set to `Id`
File size: 13.3 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Register_Address_Translation_unit_function_one_save_transition.cpp 145 2010-10-13 18:15:51Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_ooo_engine {
15	namespace ooo_engine {
16	namespace rename_unit {
17	namespace register_translation_unit {
18	namespace register_address_translation_unit {
19
20
21	#undef FUNCTION
22	#define FUNCTION "Register_Address_Translation_unit::function_one_save_transition"
23	void Register_Address_Translation_unit::function_one_save_transition (void)
24	{
25	log_begin(Register_Address_Translation_unit,FUNCTION);
26	log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str());
27
28	if (PORT_READ(in_NRESET) == 0)
29	{
30	uint32_t gpr = 1;
31	uint32_t spr = 0;
32
33	for (uint32_t i=0; i<_param->_nb_front_end; i++)
34	for (uint32_t j=0; j<_param->_nb_context[i]; j++)
35	{
36	RAT_GPR_NOT_SPECULATIVE [i][j][0] = 0;
37	RAT_GPR_SPECULATIVE_VALID [i][j][0][0] = false;
38	RAT_GPR_SPECULATIVE [i][j][0][0] = 0 ; // not necessary
39
40	for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
41	{
42	RAT_GPR_NOT_SPECULATIVE [i][j][k] = gpr++;
43	RAT_GPR_SPECULATIVE_VALID [i][j][0][k] = false;
44	RAT_GPR_SPECULATIVE [i][j][0][k] = 0 ; // not necessary
45	}
46	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
47	{
48	RAT_SPR_NOT_SPECULATIVE [i][j][k] = spr++;
49	RAT_SPR_SPECULATIVE_VALID [i][j][0][k] = false;
50	RAT_SPR_SPECULATIVE [i][j][0][k] = 0 ; // not necessary
51	}
52	}
53	}
54	else
55	{
56	// Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0)
57
58	// =====================================================
59	// ====[ RETIRE_EVENT ]=================================
60	// =====================================================
61	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
62	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
63	if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j])
64	// Test if event have just occure
65	if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)
66	{
67	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Reset Update Table");
68
69	// Reset validity table
70	for (uint32_t k=0; k<_param->_nb_general_register_logic; k++)
71	RAT_GPR_SPECULATIVE_VALID [i][j][0][k] = false;
72	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
73	RAT_SPR_SPECULATIVE_VALID [i][j][0][k] = false;
74	}
75
76	// =====================================================
77	// ====[ INSERT ]=======================================
78	// =====================================================
79	// First : interface insert
80	// this instruction is speculative !!!
81	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
82	// Test transaction
83	if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK [i])
84	{
85	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * INSERT [%d]",i);
86
87	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
88	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0;
89	Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]);
90	Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]);
91
92	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id);
93	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id);
94
95	// Test if write and modifie RAT
96	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd);
97	if (write_rd == 1)
98	{
99	Tgeneral_address_t num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [i]);
100	Tgeneral_address_t num_reg_rd_phy = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]);
101
102	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log);
103	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy);
104
105	RAT_GPR_SPECULATIVE [front_end_id][context_id][0][num_reg_rd_log] = num_reg_rd_phy;
106	RAT_GPR_SPECULATIVE_VALID [front_end_id][context_id][0][num_reg_rd_log] = true;
107	}
108
109	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re);
110	if (write_re == 1)
111	{
112	Tspecial_address_t num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [i]);
113	Tspecial_address_t num_reg_re_phy = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]);
114
115	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log);
116	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy);
117
118	RAT_SPR_SPECULATIVE [front_end_id][context_id][0][num_reg_re_log] = num_reg_re_phy;
119	RAT_SPR_SPECULATIVE_VALID [front_end_id][context_id][0][num_reg_re_log] = true;
120	}
121	}
122
123	// =====================================================
124	// ====[ RETIRE ]=======================================
125	// =====================================================
126	// Second : interface retire
127	// (because if an event on the same thread : the instruction is already renamed)
128	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
129	if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i])
130	{
131	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i);
132
133	// if no event : no effect, because the RAT content the most recently register
134	// but if they have a event (exception or miss speculation), the rat must restore the oldest value
135	// To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register
136	// the retire interface became of the Re Order Buffer, also is in program sequence !
137
138	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
139	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0;
140	Tcontrol_t write_rd = PORT_READ(in_RETIRE_WRITE_RD [i]);
141	Tcontrol_t write_re = PORT_READ(in_RETIRE_WRITE_RE [i]);
142	Tcontrol_t restore = PORT_READ(in_RETIRE_RESTORE [i]);
143
144	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id);
145	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id );
146	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore : %d",restore );
147
148	// Test if write and have not a previous update
149	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd);
150	if (write_rd == 1)
151	{
152	Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]);
153
154	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log );
155
156	if (not restore)
157	{
158	Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]);
159
160	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new);
161
162	RAT_GPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
163	}
164	}
165
166	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re);
167	if (write_re == 1)
168	{
169	Tspecial_address_t num_reg_re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]);
170
171	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log );
172
173	if (not restore)
174	{
175	Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]);
176
177	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new);
178
179	RAT_SPR_NOT_SPECULATIVE [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
180	}
181	}
182
183	}
184	}
185
186	#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true)
187	{
188	uint32_t limit = 4;
189
190	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)");
191	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
192	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
193	{
194	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j);
195
196	for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)
197	{
198	std::string str = "";
199	for (uint32_t x=0; x<limit; x++)
200	{
201	uint32_t index = k+x;
202	if (index >= _param->_nb_general_register_logic)
203	break;
204	else
205	str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) \| ",index,RAT_GPR_SPECULATIVE_VALID [i][j][0][index],RAT_GPR_SPECULATIVE [i][j][0][index],RAT_GPR_NOT_SPECULATIVE [i][j][index]);
206	}
207	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
208	}
209
210	for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit)
211	{
212	std::string str = "";
213
214	for (uint32_t x=0; x<limit; x++)
215	{
216	uint32_t index = k+x;
217	if (index >= _param->_nb_special_register_logic)
218	break;
219	else
220	str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) \| ",index,RAT_SPR_SPECULATIVE_VALID [i][j][0][index],RAT_SPR_SPECULATIVE [i][j][0][index],RAT_SPR_NOT_SPECULATIVE [i][j][index]);
221	}
222	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
223	}
224	}
225	}
226	#endif
227
228	#ifdef DEBUG_TEST
229	# if 1
230	{
231	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
232	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
233	{
234	for (uint32_t x=0; x<_param->_nb_general_register_logic; ++x)
235	for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y)
236	{
237	if (RAT_GPR_SPECULATIVE_VALID [i][j][0][x] and
238	RAT_GPR_SPECULATIVE_VALID [i][j][0][y] and
239	(RAT_GPR_SPECULATIVE[i][j][0][x] == RAT_GPR_SPECULATIVE[i][j][0][y]))
240	throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_GPR_SPECULATIVE[%d][%d][0][%d] == RAT_GPR_SPECULATIVE[%d][%d][0][%d] == %d"),i,j,x,i,j,y,RAT_GPR_SPECULATIVE[i][j][0][x]));
241	if (RAT_GPR_NOT_SPECULATIVE[i][j][x] == RAT_GPR_NOT_SPECULATIVE[i][j][y])
242	throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_GPR_NOT_SPECULATIVE[%d][%d][%d] == RAT_GPR_NOT_SPECULATIVE[%d][%d][%d] == %d"),i,j,x,i,j,y,RAT_GPR_NOT_SPECULATIVE[i][j][x]));
243
244	}
245	for (uint32_t x=0; x<_param->_nb_special_register_logic; ++x)
246	for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y)
247	{
248	if(RAT_SPR_SPECULATIVE_VALID [i][j][0][x] and
249	RAT_SPR_SPECULATIVE_VALID [i][j][0][y] and
250	(RAT_SPR_SPECULATIVE[i][j][0][x] == RAT_SPR_SPECULATIVE[i][j][0][y]))
251	throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_SPR_SPECULATIVE[%d][%d][0][%d] == RAT_SPR_SPECULATIVE[%d][%d][0][%d] == %d"),i,j,x,i,j,y,RAT_SPR_SPECULATIVE[i][j][0][x]));
252	if (RAT_SPR_NOT_SPECULATIVE[i][j][x] == RAT_SPR_NOT_SPECULATIVE[i][j][y])
253	throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, RAT_SPR_NOT_SPECULATIVE[%d][%d][%d] == RAT_SPR_NOT_SPECULATIVE[%d][%d][%d] == %d"),i,j,x,i,j,y,RAT_SPR_NOT_SPECULATIVE[i][j][x]));
254
255	}
256	}
257
258	}
259	# endif
260	#endif
261
262	log_end(Register_Address_Translation_unit,FUNCTION);
263	};
264
265	}; // end namespace register_address_translation_unit
266	}; // end namespace register_translation_unit
267	}; // end namespace rename_unit
268	}; // end namespace ooo_engine
269	}; // end namespace multi_ooo_engine
270	}; // end namespace core
271
272	}; // end namespace behavioural
273	}; // end namespace morpheo
274	#endif

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_function_one_save_transition.cpp @ 145

Download in other formats: