1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Register_Address_Translation_unit_transition.cpp 128 2009-06-26 08:43:23Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_ooo_engine { |
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15 | namespace ooo_engine { |
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16 | namespace rename_unit { |
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17 | namespace register_translation_unit { |
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18 | namespace register_address_translation_unit { |
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19 | |
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20 | |
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21 | #undef FUNCTION |
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22 | #define FUNCTION "Register_Address_Translation_unit::transition" |
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23 | void Register_Address_Translation_unit::transition (void) |
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24 | { |
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25 | log_begin(Register_Address_Translation_unit,FUNCTION); |
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26 | log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str()); |
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27 | |
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28 | if (PORT_READ(in_NRESET) == 0) |
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29 | { |
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30 | uint32_t gpr = 1; |
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31 | uint32_t spr = 0; |
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32 | |
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33 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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34 | for (uint32_t j=0; j<_param->_nb_context[i]; j++) |
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35 | { |
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36 | rat_gpr_not_speculative [i][j][0] = 0; |
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37 | rat_gpr_speculative_valid [i][j][0] = false; |
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38 | rat_gpr_speculative [i][j][0] = 0 ; // not necessary |
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39 | rat_gpr_update_table [i][j][0] = false; // not necessary |
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40 | |
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41 | for (uint32_t k=1; k<_param->_nb_general_register_logic; k++) |
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42 | { |
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43 | rat_gpr_not_speculative [i][j][k] = gpr++; |
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44 | rat_gpr_speculative_valid [i][j][k] = false; |
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45 | rat_gpr_speculative [i][j][k] = 0 ; // not necessary |
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46 | rat_gpr_update_table [i][j][k] = false; // not necessary |
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47 | } |
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48 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
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49 | { |
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50 | rat_spr_not_speculative [i][j][k] = spr++; |
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51 | rat_spr_speculative_valid [i][j][k] = false; |
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52 | rat_spr_speculative [i][j][k] = 0 ; // not necessary |
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53 | rat_spr_update_table [i][j][k] = false; // not necessary |
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54 | } |
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55 | } |
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56 | } |
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57 | else |
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58 | { |
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59 | // Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0) |
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60 | |
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61 | // ===================================================== |
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62 | // ====[ RETIRE_EVENT ]================================= |
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63 | // ===================================================== |
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64 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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65 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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66 | if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j]) |
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67 | // Test if event have just occure |
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68 | if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT) |
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69 | { |
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70 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Reset Update Table"); |
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71 | |
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72 | // Reset update_table and validity table |
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73 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k++) |
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74 | { |
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75 | rat_gpr_update_table [i][j][k] = false; |
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76 | rat_gpr_speculative_valid [i][j][k] = false; |
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77 | } |
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78 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
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79 | { |
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80 | rat_spr_update_table [i][j][k] = false; |
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81 | rat_spr_speculative_valid [i][j][k] = false; |
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82 | } |
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83 | } |
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84 | |
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85 | // ===================================================== |
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86 | // ====[ INSERT ]======================================= |
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87 | // ===================================================== |
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88 | // First : interface insert |
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89 | // this instruction is speculative !!! |
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90 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
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91 | // Test transaction |
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92 | if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK [i]) |
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93 | { |
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94 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * INSERT [%d]",i); |
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95 | |
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96 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; |
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97 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; |
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98 | Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]); |
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99 | Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]); |
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100 | |
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101 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id); |
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102 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id); |
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103 | |
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104 | // Test if write and modifie RAT |
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105 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd); |
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106 | if (write_rd == 1) |
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107 | { |
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108 | Tgeneral_address_t num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [i]); |
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109 | Tgeneral_address_t num_reg_rd_phy = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]); |
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110 | |
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111 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log); |
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112 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy); |
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113 | |
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114 | rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy; |
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115 | rat_gpr_speculative_valid [front_end_id][context_id][num_reg_rd_log] = true; |
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116 | } |
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117 | |
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118 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re); |
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119 | if (write_re == 1) |
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120 | { |
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121 | Tspecial_address_t num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [i]); |
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122 | Tspecial_address_t num_reg_re_phy = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]); |
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123 | |
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124 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log); |
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125 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy); |
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126 | |
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127 | rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy; |
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128 | rat_spr_speculative_valid [front_end_id][context_id][num_reg_re_log] = true; |
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129 | } |
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130 | } |
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131 | |
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132 | // ===================================================== |
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133 | // ====[ RETIRE ]======================================= |
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134 | // ===================================================== |
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135 | // Second : interface retire |
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136 | // (because if an event on the same thread : the instruction is already renamed) |
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137 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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138 | if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i]) |
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139 | { |
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140 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i); |
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141 | |
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142 | // if no event : no effect, because the RAT content the most recently register |
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143 | // but if they have a event (exception or miss speculation), the rat must restore the oldest value |
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144 | // To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register |
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145 | // the retire interface became of the Re Order Buffer, also is in program sequence ! |
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146 | |
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147 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; |
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148 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; |
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149 | Tcontrol_t write_rd = PORT_READ(in_RETIRE_WRITE_RD [i]); |
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150 | Tcontrol_t write_re = PORT_READ(in_RETIRE_WRITE_RE [i]); |
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151 | Tcontrol_t restore = internal_RETIRE_RESTORE [i]; |
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152 | |
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153 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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154 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id ); |
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155 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore : %d",restore ); |
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156 | |
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157 | // Test if write and have not a previous update |
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158 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd); |
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159 | if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1) |
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160 | { |
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161 | Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]); |
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162 | |
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163 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log ); |
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164 | |
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165 | if (not restore) |
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166 | { |
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167 | Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); |
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168 | |
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169 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new); |
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170 | |
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171 | rat_gpr_not_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new; |
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172 | } |
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173 | |
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174 | Tcontrol_t restore_rd = internal_RETIRE_RESTORE_RD_PHY_OLD [i]; |
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175 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore_rd : %d",restore_rd ); |
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176 | |
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177 | if (restore_rd) |
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178 | rat_gpr_update_table [front_end_id][context_id][num_reg_rd_log] = true; |
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179 | } |
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180 | |
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181 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re); |
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182 | if (PORT_READ(in_RETIRE_WRITE_RE [i]) == 1) |
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183 | { |
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184 | Tspecial_address_t num_reg_re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]); |
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185 | |
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186 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log ); |
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187 | |
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188 | if (not restore) |
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189 | { |
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190 | Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); |
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191 | |
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192 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new); |
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193 | |
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194 | rat_spr_not_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new; |
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195 | } |
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196 | |
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197 | Tcontrol_t restore_re = internal_RETIRE_RESTORE_RE_PHY_OLD [i]; |
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198 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore_re : %d",restore_re ); |
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199 | |
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200 | if (restore_re) |
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201 | rat_spr_update_table [front_end_id][context_id][num_reg_re_log] = true; |
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202 | } |
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203 | |
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204 | } |
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205 | } |
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206 | |
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207 | #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true) |
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208 | { |
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209 | uint32_t limit = 4; |
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210 | |
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211 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)"); |
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212 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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213 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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214 | { |
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215 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j); |
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216 | |
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217 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit) |
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218 | { |
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219 | std::string str = ""; |
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220 | for (uint32_t x=0; x<limit; x++) |
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221 | { |
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222 | uint32_t index = k+x; |
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223 | if (index >= _param->_nb_general_register_logic) |
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224 | break; |
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225 | else |
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226 | str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) %.1d | ",index,rat_gpr_speculative_valid [i][j][index],rat_gpr_speculative [i][j][index],rat_gpr_not_speculative [i][j][index],rat_gpr_update_table[i][j][index]); |
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227 | } |
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228 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); |
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229 | } |
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230 | |
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231 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit) |
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232 | { |
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233 | std::string str = ""; |
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234 | |
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235 | for (uint32_t x=0; x<limit; x++) |
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236 | { |
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237 | uint32_t index = k+x; |
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238 | if (index >= _param->_nb_special_register_logic) |
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239 | break; |
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240 | else |
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241 | str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) %.1d | ",index,rat_spr_speculative_valid [i][j][index],rat_spr_speculative [i][j][index],rat_spr_not_speculative [i][j][index],rat_spr_update_table[i][j][index]); |
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242 | } |
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243 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str()); |
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244 | } |
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245 | } |
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246 | } |
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247 | #endif |
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248 | |
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249 | #ifdef DEBUG_TEST |
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250 | # if 1 |
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251 | { |
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252 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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253 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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254 | { |
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255 | for (uint32_t x=0; x<_param->_nb_general_register_logic; ++x) |
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256 | for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y) |
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257 | { |
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258 | if (rat_gpr_speculative_valid [i][j][x] and |
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259 | rat_gpr_speculative_valid [i][j][y] and |
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260 | (rat_gpr_speculative[i][j][x] == rat_gpr_speculative[i][j][y])) |
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261 | throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_speculative[%d][%d][%d] == rat_gpr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_speculative[i][j][x])); |
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262 | if (rat_gpr_not_speculative[i][j][x] == rat_gpr_not_speculative[i][j][y]) |
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263 | throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_not_speculative[%d][%d][%d] == rat_gpr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_not_speculative[i][j][x])); |
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264 | |
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265 | } |
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266 | for (uint32_t x=0; x<_param->_nb_special_register_logic; ++x) |
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267 | for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y) |
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268 | { |
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269 | if(rat_spr_speculative_valid [i][j][x] and |
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270 | rat_spr_speculative_valid [i][j][y] and |
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271 | (rat_spr_speculative[i][j][x] == rat_spr_speculative[i][j][y])) |
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272 | throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_speculative[%d][%d][%d] == rat_spr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_speculative[i][j][x])); |
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273 | if (rat_spr_not_speculative[i][j][x] == rat_spr_not_speculative[i][j][y]) |
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274 | throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_not_speculative[%d][%d][%d] == rat_spr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_not_speculative[i][j][x])); |
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275 | |
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276 | } |
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277 | } |
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278 | |
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279 | } |
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280 | # endif |
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281 | #endif |
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282 | |
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283 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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284 | end_cycle (); |
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285 | #endif |
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286 | |
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287 | log_end(Register_Address_Translation_unit,FUNCTION); |
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288 | }; |
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289 | |
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290 | }; // end namespace register_address_translation_unit |
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291 | }; // end namespace register_translation_unit |
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292 | }; // end namespace rename_unit |
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293 | }; // end namespace ooo_engine |
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294 | }; // end namespace multi_ooo_engine |
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295 | }; // end namespace core |
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296 | |
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297 | }; // end namespace behavioural |
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298 | }; // end namespace morpheo |
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299 | #endif |
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