1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Register_Address_Translation_unit_transition.cpp 104 2009-01-21 21:53:13Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_ooo_engine { |
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15 | namespace ooo_engine { |
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16 | namespace rename_unit { |
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17 | namespace register_translation_unit { |
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18 | namespace register_address_translation_unit { |
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19 | |
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20 | |
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21 | #undef FUNCTION |
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22 | #define FUNCTION "Register_Address_Translation_unit::transition" |
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23 | void Register_Address_Translation_unit::transition (void) |
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24 | { |
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25 | log_begin(Register_Address_Translation_unit,FUNCTION); |
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26 | log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str()); |
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27 | |
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28 | if (PORT_READ(in_NRESET) == 0) |
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29 | { |
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30 | uint32_t gpr = 1; |
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31 | uint32_t spr = 0; |
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32 | |
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33 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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34 | for (uint32_t j=0; j<_param->_nb_context[i]; j++) |
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35 | { |
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36 | rat_gpr [i][j][0] = 0; |
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37 | |
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38 | for (uint32_t k=1; k<_param->_nb_general_register_logic; k++) |
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39 | { |
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40 | rat_gpr [i][j][k] = gpr++; |
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41 | // rat_gpr_update_table[i][j][k] = 0; |
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42 | } |
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43 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
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44 | { |
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45 | rat_spr [i][j][k] = spr++; |
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46 | // rat_spr_update_table[i][j][k] = 0; |
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47 | } |
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48 | } |
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49 | } |
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50 | else |
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51 | { |
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52 | // Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0) |
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53 | |
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54 | // ===================================================== |
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55 | // ====[ INSERT ]======================================= |
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56 | // ===================================================== |
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57 | // First : interface insert |
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58 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
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59 | // Test transaction |
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60 | if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK [i]) |
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61 | { |
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62 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * INSERT [%d]",i); |
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63 | |
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64 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0; |
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65 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0; |
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66 | |
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67 | // Test if write |
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68 | if (PORT_READ(in_INSERT_WRITE_RD [i]) == 1) |
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69 | rat_gpr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RD_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]); |
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70 | if (PORT_READ(in_INSERT_WRITE_RE [i]) == 1) |
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71 | rat_spr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RE_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]); |
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72 | } |
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73 | |
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74 | // ===================================================== |
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75 | // ====[ RETIRE_EVENT ]================================= |
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76 | // ===================================================== |
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77 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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78 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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79 | if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j]) |
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80 | // Test if event have just occure |
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81 | if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT) |
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82 | { |
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83 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Reset Update Table"); |
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84 | |
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85 | // Reset update_table |
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86 | for (uint32_t k=0; k<_param->_nb_general_register_logic; k++) |
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87 | rat_gpr_update_table [i][j][k] = 0; |
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88 | for (uint32_t k=0; k<_param->_nb_special_register_logic; k++) |
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89 | rat_spr_update_table [i][j][k] = 0; |
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90 | } |
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91 | |
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92 | // ===================================================== |
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93 | // ====[ RETIRE ]======================================= |
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94 | // ===================================================== |
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95 | // Second : interface retire |
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96 | // (because if an event on the same thread : the instruction is already renamed) |
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97 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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98 | if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i]) |
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99 | { |
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100 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i); |
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101 | |
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102 | // if no event : no effect, because the RAT content the most recently register |
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103 | // but if they have a event (exception or miss speculation), the rat must restore the oldest value |
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104 | // To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register |
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105 | // the retire interface became of the Re Order Buffer, also is in program sequence ! |
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106 | |
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107 | Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0; |
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108 | Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0; |
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109 | Tevent_state_t event_state = PORT_READ(in_RETIRE_EVENT_STATE [front_end_id][context_id]); |
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110 | |
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111 | if (event_state != EVENT_STATE_NO_EVENT) |
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112 | { |
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113 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id); |
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114 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id); |
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115 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * event_state : %d",event_state); |
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116 | |
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117 | // Test if write and have not a previous update |
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118 | if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1) |
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119 | { |
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120 | Tgeneral_address_t rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]); |
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121 | |
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122 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * retire RD"); |
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123 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * rd_log : %d",rd_log); |
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124 | |
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125 | // if (RETIRE_RESTORE_RD_PHY_OLD [i]) |
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126 | if (rat_gpr_update_table [front_end_id][context_id][rd_log] == 0) |
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127 | { |
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128 | rat_gpr [front_end_id][context_id][rd_log] = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); |
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129 | rat_gpr_update_table [front_end_id][context_id][rd_log] = 1; |
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130 | } |
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131 | } |
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132 | |
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133 | if (PORT_READ(in_RETIRE_WRITE_RE [i]) == 1) |
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134 | { |
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135 | Tspecial_address_t re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]); |
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136 | |
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137 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * retire RE"); |
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138 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * re_log : %d",re_log); |
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139 | |
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140 | // if (RETIRE_RESTORE_RE_PHY_OLD [i]) |
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141 | if (rat_spr_update_table [front_end_id][context_id][re_log] == 0) |
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142 | { |
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143 | rat_spr [front_end_id][context_id][re_log] = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); |
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144 | rat_spr_update_table [front_end_id][context_id][re_log] = 1; |
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145 | } |
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146 | } |
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147 | } |
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148 | } |
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149 | } |
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150 | |
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151 | #if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true) |
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152 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)"); |
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153 | for (uint32_t i=0; i<_param->_nb_front_end; ++i) |
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154 | for (uint32_t j=0; j<_param->_nb_context[i]; ++j) |
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155 | { |
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156 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j); |
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157 | |
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158 | for (uint32_t k=0; k<_param->_nb_general_register_logic; ++k) |
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159 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * GPR[%.4d] - %.5d %.1d",k,rat_gpr[i][j][k],rat_gpr_update_table[i][j][k]); |
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160 | |
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161 | for (uint32_t k=0; k<_param->_nb_special_register_logic; ++k) |
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162 | log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * SPR[%.4d] - %.5d %.1d",k,rat_spr[i][j][k],rat_spr_update_table[i][j][k]); |
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163 | } |
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164 | #endif |
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165 | |
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166 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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167 | end_cycle (); |
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168 | #endif |
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169 | |
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170 | log_end(Register_Address_Translation_unit,FUNCTION); |
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171 | }; |
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172 | |
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173 | }; // end namespace register_address_translation_unit |
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174 | }; // end namespace register_translation_unit |
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175 | }; // end namespace rename_unit |
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176 | }; // end namespace ooo_engine |
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177 | }; // end namespace multi_ooo_engine |
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178 | }; // end namespace core |
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179 | |
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180 | }; // end namespace behavioural |
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181 | }; // end namespace morpheo |
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182 | #endif |
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