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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp @ 122

Last change on this file since 122 was 122, checked in by rosiere, 15 years ago
Modif for performance : 1) Load Store Unit : store send request to valid exeception 2) Commit_unit : retire can bypass store 3) Commit_unit : add stat to manage store instruction 4) Load Store Unit and Load Store Pointer Manager : add store_queue_ptr_read 5) Fix lot of bug
Property svn:keywords set to `Id`
File size: 14.4 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Register_Address_Translation_unit_transition.cpp 122 2009-06-03 08:15:51Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_ooo_engine {
15	namespace ooo_engine {
16	namespace rename_unit {
17	namespace register_translation_unit {
18	namespace register_address_translation_unit {
19
20
21	#undef FUNCTION
22	#define FUNCTION "Register_Address_Translation_unit::transition"
23	void Register_Address_Translation_unit::transition (void)
24	{
25	log_begin(Register_Address_Translation_unit,FUNCTION);
26	log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str());
27
28	if (PORT_READ(in_NRESET) == 0)
29	{
30	uint32_t gpr = 1;
31	uint32_t spr = 0;
32
33	for (uint32_t i=0; i<_param->_nb_front_end; i++)
34	for (uint32_t j=0; j<_param->_nb_context[i]; j++)
35	{
36	rat_gpr_not_speculative [i][j][0] = 0;
37	rat_gpr_speculative_valid [i][j][0] = false;
38
39	for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
40	{
41	rat_gpr_not_speculative [i][j][k] = gpr++;
42	// rat_gpr_speculative [i][j][k] = gpr++;
43	rat_gpr_speculative_valid [i][j][k] = false;
44	// rat_gpr_update_table [i][j][k] = false;
45	}
46	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
47	{
48	rat_spr_not_speculative [i][j][k] = spr++;
49	// rat_spr_speculative [i][j][k] = spr++;
50	rat_spr_speculative_valid [i][j][k] = false;
51	// rat_spr_update_table [i][j][k] = false;
52	}
53	}
54	}
55	else
56	{
57	// Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0)
58
59	// =====================================================
60	// ====[ RETIRE_EVENT ]=================================
61	// =====================================================
62	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
63	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
64	if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j])
65	// Test if event have just occure
66	if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)
67	{
68	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Reset Update Table");
69
70	// Reset update_table and validity table
71	for (uint32_t k=0; k<_param->_nb_general_register_logic; k++)
72	{
73	rat_gpr_update_table [i][j][k] = false;
74	rat_gpr_speculative_valid [i][j][k] = false;
75	}
76	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
77	{
78	rat_spr_update_table [i][j][k] = false;
79	rat_spr_speculative_valid [i][j][k] = false;
80	}
81	}
82
83	// =====================================================
84	// ====[ INSERT ]=======================================
85	// =====================================================
86	// First : interface insert
87	// this instruction is speculative !!!
88	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
89	// Test transaction
90	if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK [i])
91	{
92	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * INSERT [%d]",i);
93
94	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
95	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0;
96	Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]);
97	Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]);
98
99	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id);
100	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id);
101
102	// Test if write and modifie RAT
103	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd);
104	if (write_rd == 1)
105	{
106	Tgeneral_address_t num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [i]);
107	Tgeneral_address_t num_reg_rd_phy = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]);
108
109	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log);
110	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy);
111
112	rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy;
113	rat_gpr_speculative_valid [front_end_id][context_id][num_reg_rd_log] = true;
114	}
115
116	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re);
117	if (write_re == 1)
118	{
119	Tspecial_address_t num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [i]);
120	Tspecial_address_t num_reg_re_phy = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]);
121
122	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log);
123	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy);
124
125	rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy;
126	rat_spr_speculative_valid [front_end_id][context_id][num_reg_re_log] = true;
127	}
128	}
129
130	// =====================================================
131	// ====[ RETIRE ]=======================================
132	// =====================================================
133	// Second : interface retire
134	// (because if an event on the same thread : the instruction is already renamed)
135	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
136	if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i])
137	{
138	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i);
139
140	// if no event : no effect, because the RAT content the most recently register
141	// but if they have a event (exception or miss speculation), the rat must restore the oldest value
142	// To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register
143	// the retire interface became of the Re Order Buffer, also is in program sequence !
144
145	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
146	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0;
147	Tcontrol_t write_rd = PORT_READ(in_RETIRE_WRITE_RD [i]);
148	Tcontrol_t write_re = PORT_READ(in_RETIRE_WRITE_RE [i]);
149	Tcontrol_t restore = internal_RETIRE_RESTORE [i];
150
151	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id);
152	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id );
153	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore : %d",restore );
154
155	// Test if write and have not a previous update
156	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd);
157	if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1)
158	{
159	Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]);
160
161	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log );
162
163	if (not restore)
164	{
165	Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]);
166
167	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new);
168
169	rat_gpr_not_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
170	}
171
172	Tcontrol_t restore_rd = internal_RETIRE_RESTORE_RD_PHY_OLD [i];
173	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore_rd : %d",restore_rd );
174
175	if (restore_rd)
176	rat_gpr_update_table [front_end_id][context_id][num_reg_rd_log] = true;
177	}
178
179	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re);
180	if (PORT_READ(in_RETIRE_WRITE_RE [i]) == 1)
181	{
182	Tspecial_address_t num_reg_re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]);
183
184	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log );
185
186	if (not restore)
187	{
188	Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]);
189
190	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new);
191
192	rat_spr_not_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
193	}
194
195	Tcontrol_t restore_re = internal_RETIRE_RESTORE_RE_PHY_OLD [i];
196	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore_re : %d",restore_re );
197
198	if (restore_re)
199	rat_spr_update_table [front_end_id][context_id][num_reg_re_log] = true;
200	}
201
202	}
203	}
204
205	#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true)
206	{
207	uint32_t limit = 4;
208
209	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)");
210	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
211	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
212	{
213	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j);
214
215	for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)
216	{
217	std::string str = "";
218	for (uint32_t x=0; x<limit; x++)
219	{
220	uint32_t index = k+x;
221	if (index >= _param->_nb_general_register_logic)
222	break;
223	else
224	str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) %.1d \| ",index,rat_gpr_speculative_valid [i][j][index],rat_gpr_speculative [i][j][index],rat_gpr_not_speculative [i][j][index],rat_gpr_update_table[i][j][index]);
225	}
226	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
227	}
228
229	for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit)
230	{
231	std::string str = "";
232
233	for (uint32_t x=0; x<limit; x++)
234	{
235	uint32_t index = k+x;
236	if (index >= _param->_nb_special_register_logic)
237	break;
238	else
239	str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) %.1d \| ",index,rat_spr_speculative_valid [i][j][index],rat_spr_speculative [i][j][index],rat_spr_not_speculative [i][j][index],rat_spr_update_table[i][j][index]);
240	}
241	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
242	}
243	}
244	}
245	#endif
246
247	#ifdef DEBUG_TEST
248	# if 1
249	{
250	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
251	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
252	{
253	for (uint32_t x=0; x<_param->_nb_general_register_logic; ++x)
254	for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y)
255	{
256	if (rat_gpr_speculative_valid [i][j][x] and
257	rat_gpr_speculative_valid [i][j][y] and
258	(rat_gpr_speculative[i][j][x] == rat_gpr_speculative[i][j][y]))
259	throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_speculative[%d][%d][%d] == rat_gpr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_speculative[i][j][x]));
260	if (rat_gpr_not_speculative[i][j][x] == rat_gpr_not_speculative[i][j][y])
261	throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_not_speculative[%d][%d][%d] == rat_gpr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_not_speculative[i][j][x]));
262
263	}
264	for (uint32_t x=0; x<_param->_nb_special_register_logic; ++x)
265	for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y)
266	{
267	if(rat_spr_speculative_valid [i][j][x] and
268	rat_spr_speculative_valid [i][j][y] and
269	(rat_spr_speculative[i][j][x] == rat_spr_speculative[i][j][y]))
270	throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_speculative[%d][%d][%d] == rat_spr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_speculative[i][j][x]));
271	if (rat_spr_not_speculative[i][j][x] == rat_spr_not_speculative[i][j][y])
272	throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_not_speculative[%d][%d][%d] == rat_spr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_not_speculative[i][j][x]));
273
274	}
275	}
276
277	}
278	# endif
279	#endif
280
281	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
282	end_cycle ();
283	#endif
284
285	log_end(Register_Address_Translation_unit,FUNCTION);
286	};
287
288	}; // end namespace register_address_translation_unit
289	}; // end namespace register_translation_unit
290	}; // end namespace rename_unit
291	}; // end namespace ooo_engine
292	}; // end namespace multi_ooo_engine
293	}; // end namespace core
294
295	}; // end namespace behavioural
296	}; // end namespace morpheo
297	#endif

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