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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp @ 128

Last change on this file since 128 was 128, checked in by rosiere, 15 years ago
1) Correct bug in link two signal 2) Fix error detected with valgrind 3) modif distexe script
Property svn:keywords set to `Id`
File size: 14.6 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Register_Address_Translation_unit_transition.cpp 128 2009-06-26 08:43:23Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_ooo_engine {
15	namespace ooo_engine {
16	namespace rename_unit {
17	namespace register_translation_unit {
18	namespace register_address_translation_unit {
19
20
21	#undef FUNCTION
22	#define FUNCTION "Register_Address_Translation_unit::transition"
23	void Register_Address_Translation_unit::transition (void)
24	{
25	log_begin(Register_Address_Translation_unit,FUNCTION);
26	log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str());
27
28	if (PORT_READ(in_NRESET) == 0)
29	{
30	uint32_t gpr = 1;
31	uint32_t spr = 0;
32
33	for (uint32_t i=0; i<_param->_nb_front_end; i++)
34	for (uint32_t j=0; j<_param->_nb_context[i]; j++)
35	{
36	rat_gpr_not_speculative [i][j][0] = 0;
37	rat_gpr_speculative_valid [i][j][0] = false;
38	rat_gpr_speculative [i][j][0] = 0 ; // not necessary
39	rat_gpr_update_table [i][j][0] = false; // not necessary
40
41	for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
42	{
43	rat_gpr_not_speculative [i][j][k] = gpr++;
44	rat_gpr_speculative_valid [i][j][k] = false;
45	rat_gpr_speculative [i][j][k] = 0 ; // not necessary
46	rat_gpr_update_table [i][j][k] = false; // not necessary
47	}
48	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
49	{
50	rat_spr_not_speculative [i][j][k] = spr++;
51	rat_spr_speculative_valid [i][j][k] = false;
52	rat_spr_speculative [i][j][k] = 0 ; // not necessary
53	rat_spr_update_table [i][j][k] = false; // not necessary
54	}
55	}
56	}
57	else
58	{
59	// Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0)
60
61	// =====================================================
62	// ====[ RETIRE_EVENT ]=================================
63	// =====================================================
64	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
65	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
66	if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j])
67	// Test if event have just occure
68	if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)
69	{
70	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Reset Update Table");
71
72	// Reset update_table and validity table
73	for (uint32_t k=0; k<_param->_nb_general_register_logic; k++)
74	{
75	rat_gpr_update_table [i][j][k] = false;
76	rat_gpr_speculative_valid [i][j][k] = false;
77	}
78	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
79	{
80	rat_spr_update_table [i][j][k] = false;
81	rat_spr_speculative_valid [i][j][k] = false;
82	}
83	}
84
85	// =====================================================
86	// ====[ INSERT ]=======================================
87	// =====================================================
88	// First : interface insert
89	// this instruction is speculative !!!
90	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
91	// Test transaction
92	if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK [i])
93	{
94	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * INSERT [%d]",i);
95
96	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
97	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0;
98	Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]);
99	Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]);
100
101	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id);
102	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id);
103
104	// Test if write and modifie RAT
105	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd);
106	if (write_rd == 1)
107	{
108	Tgeneral_address_t num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [i]);
109	Tgeneral_address_t num_reg_rd_phy = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]);
110
111	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log);
112	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy);
113
114	rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy;
115	rat_gpr_speculative_valid [front_end_id][context_id][num_reg_rd_log] = true;
116	}
117
118	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re);
119	if (write_re == 1)
120	{
121	Tspecial_address_t num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [i]);
122	Tspecial_address_t num_reg_re_phy = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]);
123
124	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log);
125	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy);
126
127	rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy;
128	rat_spr_speculative_valid [front_end_id][context_id][num_reg_re_log] = true;
129	}
130	}
131
132	// =====================================================
133	// ====[ RETIRE ]=======================================
134	// =====================================================
135	// Second : interface retire
136	// (because if an event on the same thread : the instruction is already renamed)
137	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
138	if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i])
139	{
140	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i);
141
142	// if no event : no effect, because the RAT content the most recently register
143	// but if they have a event (exception or miss speculation), the rat must restore the oldest value
144	// To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register
145	// the retire interface became of the Re Order Buffer, also is in program sequence !
146
147	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
148	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0;
149	Tcontrol_t write_rd = PORT_READ(in_RETIRE_WRITE_RD [i]);
150	Tcontrol_t write_re = PORT_READ(in_RETIRE_WRITE_RE [i]);
151	Tcontrol_t restore = internal_RETIRE_RESTORE [i];
152
153	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id);
154	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id );
155	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore : %d",restore );
156
157	// Test if write and have not a previous update
158	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd);
159	if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1)
160	{
161	Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]);
162
163	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log );
164
165	if (not restore)
166	{
167	Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]);
168
169	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new);
170
171	rat_gpr_not_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
172	}
173
174	Tcontrol_t restore_rd = internal_RETIRE_RESTORE_RD_PHY_OLD [i];
175	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore_rd : %d",restore_rd );
176
177	if (restore_rd)
178	rat_gpr_update_table [front_end_id][context_id][num_reg_rd_log] = true;
179	}
180
181	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re);
182	if (PORT_READ(in_RETIRE_WRITE_RE [i]) == 1)
183	{
184	Tspecial_address_t num_reg_re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]);
185
186	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log );
187
188	if (not restore)
189	{
190	Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]);
191
192	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new);
193
194	rat_spr_not_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
195	}
196
197	Tcontrol_t restore_re = internal_RETIRE_RESTORE_RE_PHY_OLD [i];
198	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore_re : %d",restore_re );
199
200	if (restore_re)
201	rat_spr_update_table [front_end_id][context_id][num_reg_re_log] = true;
202	}
203
204	}
205	}
206
207	#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true)
208	{
209	uint32_t limit = 4;
210
211	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)");
212	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
213	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
214	{
215	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d]",i,j);
216
217	for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)
218	{
219	std::string str = "";
220	for (uint32_t x=0; x<limit; x++)
221	{
222	uint32_t index = k+x;
223	if (index >= _param->_nb_general_register_logic)
224	break;
225	else
226	str+=toString("GPR[%.4d] - %.1d %.5d (%.5d) %.1d \| ",index,rat_gpr_speculative_valid [i][j][index],rat_gpr_speculative [i][j][index],rat_gpr_not_speculative [i][j][index],rat_gpr_update_table[i][j][index]);
227	}
228	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
229	}
230
231	for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit)
232	{
233	std::string str = "";
234
235	for (uint32_t x=0; x<limit; x++)
236	{
237	uint32_t index = k+x;
238	if (index >= _param->_nb_special_register_logic)
239	break;
240	else
241	str+=toString("SPR[%.4d] - %.1d %.5d (%.5d) %.1d \| ",index,rat_spr_speculative_valid [i][j][index],rat_spr_speculative [i][j][index],rat_spr_not_speculative [i][j][index],rat_spr_update_table[i][j][index]);
242	}
243	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
244	}
245	}
246	}
247	#endif
248
249	#ifdef DEBUG_TEST
250	# if 1
251	{
252	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
253	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
254	{
255	for (uint32_t x=0; x<_param->_nb_general_register_logic; ++x)
256	for (uint32_t y=x+1; y<_param->_nb_general_register_logic; ++y)
257	{
258	if (rat_gpr_speculative_valid [i][j][x] and
259	rat_gpr_speculative_valid [i][j][y] and
260	(rat_gpr_speculative[i][j][x] == rat_gpr_speculative[i][j][y]))
261	throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_speculative[%d][%d][%d] == rat_gpr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_speculative[i][j][x]));
262	if (rat_gpr_not_speculative[i][j][x] == rat_gpr_not_speculative[i][j][y])
263	throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_gpr_not_speculative[%d][%d][%d] == rat_gpr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_gpr_not_speculative[i][j][x]));
264
265	}
266	for (uint32_t x=0; x<_param->_nb_special_register_logic; ++x)
267	for (uint32_t y=x+1; y<_param->_nb_special_register_logic; ++y)
268	{
269	if(rat_spr_speculative_valid [i][j][x] and
270	rat_spr_speculative_valid [i][j][y] and
271	(rat_spr_speculative[i][j][x] == rat_spr_speculative[i][j][y]))
272	throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_speculative[%d][%d][%d] == rat_spr_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_speculative[i][j][x]));
273	if (rat_spr_not_speculative[i][j][x] == rat_spr_not_speculative[i][j][y])
274	throw ERRORMORPHEO (FUNCTION,toString(_("In RAT, rat_spr_not_speculative[%d][%d][%d] == rat_spr_not_speculative[%d][%d][%d] == %d"),i,j,x,i,j,y,rat_spr_not_speculative[i][j][x]));
275
276	}
277	}
278
279	}
280	# endif
281	#endif
282
283	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
284	end_cycle ();
285	#endif
286
287	log_end(Register_Address_Translation_unit,FUNCTION);
288	};
289
290	}; // end namespace register_address_translation_unit
291	}; // end namespace register_translation_unit
292	}; // end namespace rename_unit
293	}; // end namespace ooo_engine
294	}; // end namespace multi_ooo_engine
295	}; // end namespace core
296
297	}; // end namespace behavioural
298	}; // end namespace morpheo
299	#endif

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