source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/Register_Address_Translation_unit_transition.cpp @ 78

Last change on this file since 78 was 78, checked in by rosiere, 16 years ago

Add :

  • Execute_loop (must be test systemC)
  • Prediction
    • Direction : predifined scheme
    • Branch Target Buffer
  • iFetch_unit
    • ifetch_queue
    • pc management
  • Decod_unit
    • coming soon : support for custom operation
  • Rename_unit
    • RAT
    • Free_list
    • Dependence RAW check
    • Load store unit pointer
  • New Environnement (hierarchy_memory will remove in a next version)


Modif :

  • Manage Custom Operation
  • All component in execute_loop to use the new statistics management

Not Finish :

  • Return Address Stack
  • Environnement
File size: 5.3 KB
Line 
1#ifdef SYSTEMC
2/*
3 * $Id$
4 *
5 * [ Description ]
6 *
7 */
8
9#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_ooo_engine {
15namespace ooo_engine {
16namespace rename_unit {
17namespace register_translation_unit {
18namespace register_address_translation_unit {
19
20
21#undef  FUNCTION
22#define FUNCTION "Register_Address_Translation_unit::transition"
23  void Register_Address_Translation_unit::transition (void)
24  {
25    log_printf(FUNC,Register_Address_Translation_unit,FUNCTION,"Begin");
26
27    if (PORT_READ(in_NRESET) == 0)
28      {
29        uint32_t gpr = 1;
30        uint32_t spr = 0;
31
32        for (uint32_t i=0; i<_param->_nb_front_end; i++)
33          for (uint32_t j=0; j<_param->_nb_context[i]; j++)
34            {
35              rat_gpr [i][j][0] = 0;
36
37              for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
38                rat_gpr [i][j][k] = gpr++;
39              for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
40                rat_spr [i][j][k] = spr++;
41            }
42      }
43    else
44      {
45        // Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0)
46
47        // =====================================================
48        // ====[ INSERT ]=======================================
49        // =====================================================
50        // First : interface insert
51        for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
52          // Test transaction
53          if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK  [i])
54            {
55              Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
56              Tcontext_t context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RENAME_CONTEXT_ID   [i]):0;
57             
58              // Test if write
59              if (PORT_READ(in_INSERT_WRITE_RD [i]) == 1)
60                rat_gpr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RD_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]);
61              if (PORT_READ(in_INSERT_WRITE_RE [i]) == 1)
62                rat_spr[front_end_id][context_id][PORT_READ(in_INSERT_NUM_REG_RE_LOG [i])] = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]);
63            }
64
65        // =====================================================
66        // ====[ RETIRE ]=======================================
67        // =====================================================
68        // Second : interface retire
69        //  (because if an event on the same thread : the instruction is already renamed)
70        for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
71          if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i])
72            {
73              // if no event : no effect, because the RAT content the most recently register
74              // but if they have a event (exception or miss speculation), the rat must restore the oldest value
75              // To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register
76              // the retire interface became of the Re Order Buffer, also is in program sequence !
77              if (PORT_READ(in_RETIRE_EVENT_STATE [i]) != EVENT_STATE_NO_EVENT)
78                {
79                  Tcontext_t         front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
80                  Tcontext_t         context_id   = (_param->_have_port_context_id  )?PORT_READ(in_RETIRE_CONTEXT_ID   [i]):0;
81
82                  // Test if event have just occure
83                  if (PORT_READ(in_RETIRE_EVENT_STATE [i]) == EVENT_STATE_EVENT)
84                    {
85                      // Reset update_table
86                      for (uint32_t j=0; j<_param->_nb_general_register_logic; j++)
87                        rat_gpr_update_table[front_end_id][context_id][j] = 0;
88                      for (uint32_t j=0; j<_param->_nb_special_register_logic; j++)
89                        rat_spr_update_table[front_end_id][context_id][j] = 0;
90                    }
91
92 
93                  // Test if write and have not a previous update
94                  if (PORT_READ(in_RETIRE_WRITE_RD [i]) == 1)
95                    {
96                      Tgeneral_address_t rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]);
97                     
98                      log_printf(NONE,Register_Address_Translation_unit,FUNCTION,"retire[%d]",i);
99                      log_printf(NONE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id);
100                      log_printf(NONE,Register_Address_Translation_unit,FUNCTION," * context_id   : %d",context_id  );
101                      log_printf(NONE,Register_Address_Translation_unit,FUNCTION," * rd_log       : %d",rd_log      );
102                     
103                      if (rat_gpr_update_table[front_end_id][context_id][rd_log] == 0)
104                        {
105                          rat_gpr             [front_end_id][context_id][rd_log] = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]);
106                          rat_gpr_update_table[front_end_id][context_id][rd_log] = 1;
107                        }
108                    }
109
110                  if (PORT_READ(in_RETIRE_WRITE_RE [i]) == 1)
111                    {
112                      Tspecial_address_t re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]);
113
114                      if (rat_spr_update_table[front_end_id][context_id][re_log] == 0)
115                        {
116                          rat_spr             [front_end_id][context_id][re_log] = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]);
117                          rat_spr_update_table[front_end_id][context_id][re_log] = 1;
118                        }
119                    }
120                }
121            }
122      }
123
124#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
125    end_cycle ();
126#endif
127
128    log_printf(FUNC,Register_Address_Translation_unit,FUNCTION,"End");
129  };
130
131}; // end namespace register_address_translation_unit
132}; // end namespace register_translation_unit
133}; // end namespace rename_unit
134}; // end namespace ooo_engine
135}; // end namespace multi_ooo_engine
136}; // end namespace core
137
138}; // end namespace behavioural
139}; // end namespace morpheo             
140#endif
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