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Register_Address_Translation_unit_function_depth_save_transition.cpp @ 145

Last change on this file since 145 was 145, checked in by rosiere, 14 years ago
1) add test with SPECINT2K 2) new config of Selftest 3) modif RAT to support multiple depth_save ... but not finish (need fix Update Prediction Table) 4) add Function_pointer but need fix
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File size: 15.1 KB

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1	#ifdef SYSTEMC
2	/*
3	* $Id: Register_Address_Translation_unit_function_depth_save_transition.cpp 145 2010-10-13 18:15:51Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/include/Register_Address_Translation_unit.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_ooo_engine {
15	namespace ooo_engine {
16	namespace rename_unit {
17	namespace register_translation_unit {
18	namespace register_address_translation_unit {
19
20
21	#undef FUNCTION
22	#define FUNCTION "Register_Address_Translation_unit::function_depth_save_transition"
23	void Register_Address_Translation_unit::function_depth_save_transition (void)
24	{
25	log_begin(Register_Address_Translation_unit,FUNCTION);
26	log_function(Register_Address_Translation_unit,FUNCTION,_name.c_str());
27
28	if (PORT_READ(in_NRESET) == 0)
29	{
30	uint32_t gpr = 1;
31	uint32_t spr = 0;
32
33	for (uint32_t i=0; i<_param->_nb_front_end; i++)
34	for (uint32_t j=0; j<_param->_nb_context[i]; j++)
35	{
36	rat_depth [i][j] = 0;
37	rat_gpr_speculative [i][j][0] = 0;
38
39	for (uint32_t k=1; k<_param->_nb_general_register_logic; k++)
40	rat_gpr_speculative [i][j][k] = gpr++;
41	for (uint32_t k=0; k<_param->_nb_special_register_logic; k++)
42	rat_spr_speculative [i][j][k] = spr++; // not necessary
43	}
44	}
45	else
46	{
47	// Note : GPR[0] is never write (in decod's stage : write_rd = 0 when num_reg_rd_log == 0)
48
49	// =====================================================
50	// ====[ RETIRE_EVENT ]=================================
51	// =====================================================
52	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
53	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
54	if (PORT_READ(in_RETIRE_EVENT_VAL [i][j]) and internal_RETIRE_EVENT_ACK [i][j])
55	{
56	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE_EVENT [%d][%d]",i,j);
57
58	// Test if event have just occure
59	if (PORT_READ(in_RETIRE_EVENT_STATE [i][j]) == EVENT_STATE_EVENT)
60	{
61	switch (PORT_READ(in_RETIRE_EVENT_TYPE [i][j]))
62	{
63	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
64	case EVENT_TYPE_LOAD_MISS_SPECULATION :
65	{
66	// Miss speculation (branch or load)
67	// Restore contexte and update depth
68
69	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * MISS_SPECULATION : Restore RAT");
70
71	Tdepth_t depth = (_param->_have_port_depth)?PORT_READ(in_RETIRE_EVENT_DEPTH [i][j]):0;
72
73	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth : %d",depth);
74
75	// restore GPR
76	for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++)
77	rat_gpr_speculative [i][j][num_gpr] = rat_gpr_save [i][j][depth][num_gpr];
78
79	// restore SPR
80	for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++)
81	rat_spr_speculative [i][j][num_spr] = rat_spr_save [i][j][depth][num_spr];
82
83	// update rat_depth
84	rat_depth[i][j] = depth;
85
86	break;
87	}
88	// case EVENT_TYPE_EXCEPTION :
89	// case EVENT_TYPE_SPR_ACCESS :
90	// case EVENT_TYPE_MSYNC :
91	// case EVENT_TYPE_PSYNC :
92	// case EVENT_TYPE_CSYNC :
93	default :
94	{
95	// nothing
96	break;
97	}
98	}
99
100	}
101	}
102
103	// =====================================================
104	// ====[ INSERT ]=======================================
105	// =====================================================
106	// First : interface insert
107	// this instruction is speculative !!!
108	for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
109	// Test transaction
110	if (PORT_READ(in_INSERT_VAL [i]) and internal_INSERT_ACK [i])
111	{
112	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * INSERT [%d]",i);
113
114	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RENAME_FRONT_END_ID [i]):0;
115	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RENAME_CONTEXT_ID [i]):0;
116	Tcontrol_t save = internal_RENAME_SAVE [i];
117
118	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end : %d",front_end_id);
119	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context : %d",context_id);
120	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * save : %d",save);
121
122	// Test if write and modifie RAT (RD and RE)
123
124	Tcontrol_t write_rd = PORT_READ(in_INSERT_WRITE_RD [i]);
125	Tcontrol_t write_re = PORT_READ(in_INSERT_WRITE_RE [i]);
126
127	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd);
128	if (write_rd == 1)
129	{
130	Tgeneral_address_t num_reg_rd_log = PORT_READ(in_INSERT_NUM_REG_RD_LOG [i]);
131	Tgeneral_address_t num_reg_rd_phy = PORT_READ(in_INSERT_NUM_REG_RD_PHY [i]);
132
133	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log);
134	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy : %d",num_reg_rd_phy);
135
136	rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy;
137	}
138
139	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re);
140	if (write_re == 1)
141	{
142	Tspecial_address_t num_reg_re_log = PORT_READ(in_INSERT_NUM_REG_RE_LOG [i]);
143	Tspecial_address_t num_reg_re_phy = PORT_READ(in_INSERT_NUM_REG_RE_PHY [i]);
144
145	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log);
146	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy : %d",num_reg_re_phy);
147
148	rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy;
149	}
150
151	if (save)
152	{
153	// Need save RAT
154
155	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_RENAME_DEPTH [i]):0;
156
157	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * depth old - new : %d",depth);
158
159	// #ifdef DEBUG_TEST
160	// if (depth != ((depth_old+1)%_param->_nb_branch_speculated[front_end_id][context_id]))
161	// throw ERRORMORPHEO(FUNCTION,toString(_("Rename : Invalid depth (old : %d, new : %d).\n"),depth_old,depth));
162	// #endif
163
164	// save GPR
165	for (uint32_t num_gpr=0; num_gpr<_param->_nb_general_register_logic; num_gpr++)
166	rat_gpr_save [front_end_id][context_id][depth][num_gpr] = rat_gpr_speculative [front_end_id][context_id][num_gpr];
167
168	// save SPR
169	for (uint32_t num_spr=0; num_spr<_param->_nb_special_register_logic; num_spr++)
170	rat_spr_save [front_end_id][context_id][depth][num_spr] = rat_spr_speculative [front_end_id][context_id][num_spr];
171
172	// update rat_depth with new depth
173	rat_depth[front_end_id][context_id] = depth;
174	}
175	}
176
177	// =====================================================
178	// ====[ RETIRE ]=======================================
179	// =====================================================
180	// Second : interface retire
181	// (because if an event on the same thread : the instruction is already renamed)
182	for (uint32_t i=0; i<_param->_nb_inst_retire; i++)
183	if (PORT_READ(in_RETIRE_VAL [i]) and internal_RETIRE_ACK [i])
184	{
185	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * RETIRE [%d]",i);
186
187	// if no event : no effect, because the RAT content the most recently register
188	// but if they have a event (exception or miss speculation), the rat must restore the oldest value
189	// To restore the oldest valid value, we use the rat_update_table. if the bit is unset, also they have none update on this register
190	// the retire interface became of the Re Order Buffer, also is in program sequence !
191
192	#ifdef DEBUG
193	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_RETIRE_FRONT_END_ID [i]):0;
194	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_RETIRE_CONTEXT_ID [i]):0;
195	#endif
196	Tcontrol_t write_rd = PORT_READ(in_RETIRE_WRITE_RD [i]);
197	Tcontrol_t write_re = PORT_READ(in_RETIRE_WRITE_RE [i]);
198	Tcontrol_t restore = PORT_READ(in_RETIRE_RESTORE [i]);
199
200	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end_id : %d",front_end_id);
201	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * context_id : %d",context_id );
202	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * restore : %d",restore );
203
204	// Test if write and have not a previous update
205	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_rd : %d",write_rd);
206	if (write_rd == 1)
207	{
208	#ifdef DEBUG
209	Tgeneral_address_t num_reg_rd_log = PORT_READ(in_RETIRE_NUM_REG_RD_LOG [i]);
210	#endif
211
212	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_log : %d",num_reg_rd_log );
213
214	if (not restore)
215	{
216	#ifdef DEBUG
217	Tgeneral_address_t num_reg_rd_phy_new = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]);
218	#endif
219	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_rd_phy_new : %d",num_reg_rd_phy_new);
220
221	// rat_gpr_speculative [front_end_id][context_id][num_reg_rd_log] = num_reg_rd_phy_new;
222	}
223	}
224
225	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * write_re : %d",write_re);
226	if (write_re == 1)
227	{
228	#ifdef DEBUG
229	Tspecial_address_t num_reg_re_log = PORT_READ(in_RETIRE_NUM_REG_RE_LOG [i]);
230	#endif
231
232	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_log : %d",num_reg_re_log );
233
234	if (not restore)
235	{
236	#ifdef DEBUG
237	Tspecial_address_t num_reg_re_phy_new = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]);
238	#endif
239
240	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * num_reg_re_phy_new : %d",num_reg_re_phy_new);
241
242	// rat_spr_speculative [front_end_id][context_id][num_reg_re_log] = num_reg_re_phy_new;
243	}
244	}
245
246	}
247	}
248
249	#if (DEBUG >= DEBUG_TRACE) and (DEBUG_Register_Address_Translation_unit == true)
250	{
251	uint32_t limit = 4;
252
253	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * Dump RAT (Register_Address_Translation_unit)");
254	for (uint32_t i=0; i<_param->_nb_front_end; ++i)
255	for (uint32_t j=0; j<_param->_nb_context[i]; ++j)
256	{
257	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * front_end[%d].context[%d] - rat_depth : %d",i,j,rat_depth[i][j]);
258
259	for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)
260	{
261	std::string str = "";
262	for (uint32_t x=0; x<limit; x++)
263	{
264	uint32_t index = k+x;
265	if (index >= _param->_nb_general_register_logic)
266	break;
267	else
268	str+=toString("GPR[%.4d] - %.5d \| ",index,rat_gpr_speculative [i][j][index]);
269	}
270	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
271	}
272
273	for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
274	for (uint32_t k=0; k<_param->_nb_general_register_logic; k+=limit)
275	{
276	std::string str = "";
277	for (uint32_t x=0; x<limit; x++)
278	{
279	uint32_t index = k+x;
280	if (index >= _param->_nb_general_register_logic)
281	break;
282	else
283	str+=toString("GPR_%d[%.4d] - %.5d \| ",l,index,rat_gpr_save [i][j][l][index]);
284	}
285	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
286	}
287
288	for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit)
289	{
290	std::string str = "";
291
292	for (uint32_t x=0; x<limit; x++)
293	{
294	uint32_t index = k+x;
295	if (index >= _param->_nb_special_register_logic)
296	break;
297	else
298	str+=toString("SPR[%.4d] - %.5d \| ",index,rat_spr_speculative [i][j][index]);
299	}
300	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
301	}
302
303	for (uint32_t l=0; l<_param->_nb_branch_speculated[i][j]; ++l)
304	for (uint32_t k=0; k<_param->_nb_special_register_logic; k+=limit)
305	{
306	std::string str = "";
307	for (uint32_t x=0; x<limit; x++)
308	{
309	uint32_t index = k+x;
310	if (index >= _param->_nb_special_register_logic)
311	break;
312	else
313	str+=toString("SPR_%d[%.4d] - %.5d \| ",l,index,rat_spr_save [i][j][l][index]);
314	}
315	log_printf(TRACE,Register_Address_Translation_unit,FUNCTION," * %s",str.c_str());
316	}
317
318	}
319	}
320	#endif
321
322	log_end(Register_Address_Translation_unit,FUNCTION);
323	};
324
325	}; // end namespace register_address_translation_unit
326	}; // end namespace register_translation_unit
327	}; // end namespace rename_unit
328	}; // end namespace ooo_engine
329	}; // end namespace multi_ooo_engine
330	}; // end namespace core
331
332	}; // end namespace behavioural
333	}; // end namespace morpheo
334	#endif

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_Address_Translation_unit/src/old/Register_Address_Translation_unit_function_depth_save_transition.cpp @ 145

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