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test.cpp @ 117

Last change on this file since 117 was 117, checked in by rosiere, 15 years ago
1) Platforms : add new organization for test 2) Load_Store_Unit : add array to count nb_check in store_queue 3) Issue_queue and Core_Glue : rewrite the issue network 4) Special_Register_Unit : add reset value to register CID 5) Softwares : add multicontext test 6) Softwares : add SPECINT 7) Softwares : add MiBench? 7) Read_queue : inhib access for r0 8) Change Core_Glue (network) - dont yet support priority and load balancing scheme
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File size: 30.4 KB

Line
1	/*
2	* $Id: test.cpp 117 2009-05-16 14:42:39Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 256
10	#define CYCLE_MAX (128*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Behavioural/include/Allocation.h"
15
16	void test (string name,
17	morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::register_translation_unit_glue::Parameters * _param)
18	{
19	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
20
21	#ifdef STATISTICS
22	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
23	#endif
24
25	Tusage_t _usage = USE_ALL;
26
27	// _usage = usage_unset(_usage,USE_SYSTEMC );
28	// _usage = usage_unset(_usage,USE_VHDL );
29	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
30	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
31	// _usage = usage_unset(_usage,USE_POSITION );
32	// _usage = usage_unset(_usage,USE_STATISTICS );
33	// _usage = usage_unset(_usage,USE_INFORMATION );
34
35	Register_translation_unit_Glue * _Register_translation_unit_Glue = new Register_translation_unit_Glue
36	(name.c_str(),
37	#ifdef STATISTICS
38	_parameters_statistics,
39	#endif
40	_param,
41	_usage);
42
43	#ifdef SYSTEMC
44	/*********************************************************************
45	* Déclarations des signaux
46	*********************************************************************/
47	string rename;
48
49	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
50	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
51
52	ALLOC1_SC_SIGNAL( in_INSERT_RENAME_VAL ," in_INSERT_RENAME_VAL ",Tcontrol_t,_param->_nb_inst_insert);
53	ALLOC1_SC_SIGNAL(out_INSERT_RENAME_ACK ,"out_INSERT_RENAME_ACK ",Tcontrol_t,_param->_nb_inst_insert);
54	ALLOC1_SC_SIGNAL(out_INSERT_INSERT_VAL ,"out_INSERT_INSERT_VAL ",Tcontrol_t,_param->_nb_inst_insert);
55	ALLOC1_SC_SIGNAL( in_INSERT_INSERT_ACK ," in_INSERT_INSERT_ACK ",Tcontrol_t,_param->_nb_inst_insert);
56	ALLOC1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL ,"out_INSERT_RAT_INSERT_VAL ",Tcontrol_t,_param->_nb_inst_insert);
57	ALLOC1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK ," in_INSERT_RAT_RENAME_ACK ",Tcontrol_t,_param->_nb_inst_insert);
58	ALLOC1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK ," in_INSERT_RAT_INSERT_ACK ",Tcontrol_t,_param->_nb_inst_insert);
59	ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL ,"out_INSERT_FREE_LIST_VAL ",Tcontrol_t,_param->_nb_inst_insert);
60	ALLOC1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK ," in_INSERT_FREE_LIST_ACK ",Tcontrol_t,_param->_nb_inst_insert);
61	ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_GPR_VAL ,"out_INSERT_FREE_LIST_GPR_VAL ",Tcontrol_t,_param->_nb_inst_insert);
62	ALLOC1_SC_SIGNAL(out_INSERT_FREE_LIST_SPR_VAL ,"out_INSERT_FREE_LIST_SPR_VAL ",Tcontrol_t,_param->_nb_inst_insert);
63	ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL ,"out_INSERT_STAT_LIST_VAL ",Tcontrol_t,_param->_nb_inst_insert);
64	ALLOC1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK ," in_INSERT_STAT_LIST_ACK ",Tcontrol_t,_param->_nb_inst_insert);
65
66	ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RA ," in_INSERT_DEPENDENCY_CHECKING_READ_RA ",Tcontrol_t ,_param->_nb_inst_insert);
67	ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RA_PHY ," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_insert);
68	ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RB ," in_INSERT_DEPENDENCY_CHECKING_READ_RB ",Tcontrol_t ,_param->_nb_inst_insert);
69	ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RB_PHY ," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_insert);
70	ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RC ," in_INSERT_DEPENDENCY_CHECKING_READ_RC ",Tcontrol_t ,_param->_nb_inst_insert);
71	ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RC_PHY ," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_insert);
72	ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_WRITE_RD ," in_INSERT_DEPENDENCY_CHECKING_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_insert);
73	ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG ," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG ",Tgeneral_address_t,_param->_nb_inst_insert);
74	ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD",Tgeneral_address_t,_param->_nb_inst_insert);
75	ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW",Tgeneral_address_t,_param->_nb_inst_insert);
76	ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_WRITE_RE ," in_INSERT_DEPENDENCY_CHECKING_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_insert);
77	ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG ," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG ",Tspecial_address_t,_param->_nb_inst_insert);
78	ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD",Tspecial_address_t,_param->_nb_inst_insert);
79	ALLOC1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW," in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_nb_inst_insert);
80
81	//ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RA ,"out_INSERT_STAT_LIST_READ_RA ",Tcontrol_t ,_param->_nb_inst_insert);
82	//ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RA_PHY ,"out_INSERT_STAT_LIST_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_insert);
83	//ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RB ,"out_INSERT_STAT_LIST_READ_RB ",Tcontrol_t ,_param->_nb_inst_insert);
84	//ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RB_PHY ,"out_INSERT_STAT_LIST_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_insert);
85	//ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RC ,"out_INSERT_STAT_LIST_READ_RC ",Tcontrol_t ,_param->_nb_inst_insert);
86	//ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RC_PHY ,"out_INSERT_STAT_LIST_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_insert);
87	ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_WRITE_RD ,"out_INSERT_STAT_LIST_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_insert);
88	ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_OLD ,"out_INSERT_STAT_LIST_NUM_REG_RD_PHY_OLD ",Tgeneral_address_t,_param->_nb_inst_insert);
89	ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ,"out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t,_param->_nb_inst_insert);
90	ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_WRITE_RE ,"out_INSERT_STAT_LIST_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_insert);
91	ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_OLD ,"out_INSERT_STAT_LIST_NUM_REG_RE_PHY_OLD ",Tspecial_address_t,_param->_nb_inst_insert);
92	ALLOC1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ,"out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ",Tspecial_address_t,_param->_nb_inst_insert);
93
94	ALLOC1_SC_SIGNAL(out_INSERT_RAT_WRITE_RD ,"out_INSERT_RAT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_insert);
95	ALLOC1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RD_LOG ,"out_INSERT_RAT_NUM_REG_RD_LOG ",Tgeneral_address_t,_param->_nb_inst_insert);
96	ALLOC1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RD_PHY_NEW ,"out_INSERT_RAT_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t,_param->_nb_inst_insert);
97	ALLOC1_SC_SIGNAL(out_INSERT_RAT_WRITE_RE ,"out_INSERT_RAT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_insert);
98	ALLOC1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RE_LOG ,"out_INSERT_RAT_NUM_REG_RE_LOG ",Tspecial_address_t,_param->_nb_inst_insert);
99	ALLOC1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RE_PHY_NEW ,"out_INSERT_RAT_NUM_REG_RE_PHY_NEW ",Tspecial_address_t,_param->_nb_inst_insert);
100
101	ALLOC1_SC_SIGNAL(out_INSERT_READ_RA ,"out_INSERT_READ_RA ",Tcontrol_t ,_param->_nb_inst_insert);
102	ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RA_PHY ,"out_INSERT_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_insert);
103	ALLOC1_SC_SIGNAL(out_INSERT_READ_RB ,"out_INSERT_READ_RB ",Tcontrol_t ,_param->_nb_inst_insert);
104	ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RB_PHY ,"out_INSERT_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_insert);
105	ALLOC1_SC_SIGNAL(out_INSERT_READ_RC ,"out_INSERT_READ_RC ",Tcontrol_t ,_param->_nb_inst_insert);
106	ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RC_PHY ,"out_INSERT_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_insert);
107	ALLOC1_SC_SIGNAL(out_INSERT_WRITE_RD ,"out_INSERT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_insert);
108	ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RD_LOG ,"out_INSERT_NUM_REG_RD_LOG ",Tgeneral_address_t,_param->_nb_inst_insert);
109	ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RD_PHY_OLD ,"out_INSERT_NUM_REG_RD_PHY_OLD ",Tgeneral_address_t,_param->_nb_inst_insert);
110	ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RD_PHY_NEW ,"out_INSERT_NUM_REG_RD_PHY_NEW ",Tgeneral_address_t,_param->_nb_inst_insert);
111	ALLOC1_SC_SIGNAL(out_INSERT_WRITE_RE ,"out_INSERT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_insert);
112	ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RE_LOG ,"out_INSERT_NUM_REG_RE_LOG ",Tspecial_address_t,_param->_nb_inst_insert);
113	ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RE_PHY_OLD ,"out_INSERT_NUM_REG_RE_PHY_OLD ",Tspecial_address_t,_param->_nb_inst_insert);
114	ALLOC1_SC_SIGNAL(out_INSERT_NUM_REG_RE_PHY_NEW ,"out_INSERT_NUM_REG_RE_PHY_NEW ",Tspecial_address_t,_param->_nb_inst_insert);
115
116	ALLOC1_SC_SIGNAL( in_RETIRE_VAL ," in_RETIRE_VAL ",Tcontrol_t,_param->_nb_inst_retire);
117	ALLOC1_SC_SIGNAL(out_RETIRE_ACK ,"out_RETIRE_ACK ",Tcontrol_t,_param->_nb_inst_retire);
118	ALLOC1_SC_SIGNAL(out_RETIRE_RAT_VAL ,"out_RETIRE_RAT_VAL ",Tcontrol_t,_param->_nb_inst_retire);
119	ALLOC1_SC_SIGNAL( in_RETIRE_RAT_ACK ," in_RETIRE_RAT_ACK ",Tcontrol_t,_param->_nb_inst_retire);
120	ALLOC1_SC_SIGNAL(out_RETIRE_STAT_LIST_VAL ,"out_RETIRE_STAT_LIST_VAL ",Tcontrol_t,_param->_nb_inst_retire);
121	ALLOC1_SC_SIGNAL( in_RETIRE_STAT_LIST_ACK ," in_RETIRE_STAT_LIST_ACK ",Tcontrol_t,_param->_nb_inst_retire);
122
123	/********************************************************
124	* Instanciation
125	********************************************************/
126
127	msg(_("<%s> : Instanciation of _Register_translation_unit_Glue.\n"),name.c_str());
128
129	((_Register_translation_unit_Glue->in_CLOCK)) ((in_CLOCK));
130	((_Register_translation_unit_Glue->in_NRESET)) ((in_NRESET));
131
132	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RENAME_VAL ,_param->_nb_inst_insert);
133	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RENAME_ACK ,_param->_nb_inst_insert);
134	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_INSERT_VAL ,_param->_nb_inst_insert);
135	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_INSERT_ACK ,_param->_nb_inst_insert);
136	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_INSERT_VAL ,_param->_nb_inst_insert);
137	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RAT_RENAME_ACK ,_param->_nb_inst_insert);
138	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_RAT_INSERT_ACK ,_param->_nb_inst_insert);
139	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert);
140	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert);
141	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_GPR_VAL ,_param->_nb_inst_insert);
142	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_FREE_LIST_SPR_VAL ,_param->_nb_inst_insert);
143	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert);
144	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert);
145
146	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_READ_RA ,_param->_nb_inst_insert);
147	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RA_PHY ,_param->_nb_inst_insert);
148	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_READ_RB ,_param->_nb_inst_insert);
149	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RB_PHY ,_param->_nb_inst_insert);
150	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_READ_RC ,_param->_nb_inst_insert);
151	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RC_PHY ,_param->_nb_inst_insert);
152	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_WRITE_RD ,_param->_nb_inst_insert);
153	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG ,_param->_nb_inst_insert);
154	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert);
155	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert);
156	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_WRITE_RE ,_param->_nb_inst_insert);
157	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG ,_param->_nb_inst_insert);
158	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert);
159	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert);
160
161	//INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_READ_RA ,_param->_nb_inst_insert);
162	//INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RA_PHY ,_param->_nb_inst_insert);
163	//INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_READ_RB ,_param->_nb_inst_insert);
164	//INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RB_PHY ,_param->_nb_inst_insert);
165	//INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_READ_RC ,_param->_nb_inst_insert);
166	//INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RC_PHY ,_param->_nb_inst_insert);
167	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_WRITE_RD ,_param->_nb_inst_insert);
168	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert);
169	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert);
170	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_WRITE_RE ,_param->_nb_inst_insert);
171	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert);
172	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert);
173
174	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_WRITE_RD ,_param->_nb_inst_insert);
175	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_NUM_REG_RD_LOG ,_param->_nb_inst_insert);
176	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert);
177	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_WRITE_RE ,_param->_nb_inst_insert);
178	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_NUM_REG_RE_LOG ,_param->_nb_inst_insert);
179	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_RAT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert);
180
181	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_READ_RA ,_param->_nb_inst_insert);
182	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert);
183	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_READ_RB ,_param->_nb_inst_insert);
184	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert);
185	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_READ_RC ,_param->_nb_inst_insert);
186	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert);
187	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_WRITE_RD ,_param->_nb_inst_insert);
188	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RD_LOG ,_param->_nb_inst_insert);
189	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert);
190	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert);
191	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_WRITE_RE ,_param->_nb_inst_insert);
192	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RE_LOG ,_param->_nb_inst_insert);
193	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert);
194	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert);
195
196	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_RETIRE_VAL ,_param->_nb_inst_retire);
197	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_RETIRE_ACK ,_param->_nb_inst_retire);
198	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_RETIRE_RAT_VAL ,_param->_nb_inst_retire);
199	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_RETIRE_RAT_ACK ,_param->_nb_inst_retire);
200	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue,out_RETIRE_STAT_LIST_VAL,_param->_nb_inst_retire);
201	INSTANCE1_SC_SIGNAL(_Register_translation_unit_Glue, in_RETIRE_STAT_LIST_ACK,_param->_nb_inst_retire);
202
203	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
204
205	Time * _time = new Time();
206
207	/********************************************************
208	* Simulation - Begin
209	********************************************************/
210
211	// Initialisation
212
213	const uint32_t seed = 0;
214	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
215
216	srand(seed);
217
218	SC_START(0);
219	LABEL("Initialisation");
220
221	LABEL("Reset");
222	in_NRESET->write(0);
223	SC_START(5);
224	in_NRESET->write(1);
225
226	LABEL("Loop of Test");
227
228	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
229	{
230	LABEL("Iteration %d",iteration);
231
232	for (uint32_t i=0; i<_param->_nb_inst_insert;i++)
233	{
234	in_INSERT_RENAME_VAL [i]->write(rand()%2);
235	in_INSERT_INSERT_ACK [i]->write(rand()%2);
236	in_INSERT_RAT_RENAME_ACK[i]->write(rand()%2);
237	in_INSERT_RAT_INSERT_ACK[i]->write(rand()%2);
238	in_INSERT_FREE_LIST_ACK [i]->write(rand()%2);
239	in_INSERT_STAT_LIST_ACK [i]->write(rand()%2);
240	}
241
242	for (uint32_t i=0; i<_param->_nb_inst_retire;i++)
243	{
244	in_RETIRE_VAL [i]->write(rand()%2);
245	in_RETIRE_RAT_ACK [i]->write(rand()%2);
246	in_RETIRE_STAT_LIST_ACK [i]->write(rand()%2);
247	}
248
249	SC_START(0);
250
251	for (uint32_t i=0; i<_param->_nb_inst_insert;i++)
252	{
253	TEST(Tcontrol_t,out_INSERT_RENAME_ACK [i]->read(),(in_INSERT_INSERT_ACK [i]->read() and
254	in_INSERT_RAT_RENAME_ACK [i]->read() and
255	in_INSERT_RAT_INSERT_ACK [i]->read() and
256	in_INSERT_FREE_LIST_ACK [i]->read() and
257	in_INSERT_STAT_LIST_ACK [i]->read() ));
258	TEST(Tcontrol_t,out_INSERT_INSERT_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and
259	in_INSERT_RAT_RENAME_ACK [i]->read() and
260	in_INSERT_RAT_INSERT_ACK [i]->read() and
261	in_INSERT_FREE_LIST_ACK [i]->read() and
262	in_INSERT_STAT_LIST_ACK [i]->read() ));
263	TEST(Tcontrol_t,out_INSERT_RAT_INSERT_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and
264	in_INSERT_INSERT_ACK [i]->read() and
265	in_INSERT_RAT_RENAME_ACK [i]->read() and
266	in_INSERT_FREE_LIST_ACK [i]->read() and
267	in_INSERT_STAT_LIST_ACK [i]->read() ));
268	TEST(Tcontrol_t,out_INSERT_FREE_LIST_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and
269	in_INSERT_INSERT_ACK [i]->read() and
270	in_INSERT_RAT_RENAME_ACK [i]->read() and
271	in_INSERT_RAT_INSERT_ACK [i]->read() and
272	in_INSERT_STAT_LIST_ACK [i]->read() ));
273	TEST(Tcontrol_t,out_INSERT_FREE_LIST_GPR_VAL [i]->read(),(in_INSERT_DEPENDENCY_CHECKING_WRITE_RD[i]->read() and
274	(in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG[i]->read()!=0)));
275	TEST(Tcontrol_t,out_INSERT_FREE_LIST_SPR_VAL [i]->read(),(in_INSERT_DEPENDENCY_CHECKING_WRITE_RE[i]->read()));
276	TEST(Tcontrol_t,out_INSERT_STAT_LIST_VAL [i]->read(),(in_INSERT_RENAME_VAL [i]->read() and
277	in_INSERT_INSERT_ACK [i]->read() and
278	in_INSERT_RAT_RENAME_ACK [i]->read() and
279	in_INSERT_RAT_INSERT_ACK [i]->read() and
280	in_INSERT_FREE_LIST_ACK [i]->read() ));
281	}
282
283	for (uint32_t i=0; i<_param->_nb_inst_retire;i++)
284	{
285	TEST(Tcontrol_t,out_RETIRE_ACK [i]->read(),(in_RETIRE_RAT_ACK [i]->read() and
286	in_RETIRE_STAT_LIST_ACK [i]->read()));
287	TEST(Tcontrol_t,out_RETIRE_RAT_VAL [i]->read(),(in_RETIRE_VAL [i]->read() and
288	in_RETIRE_STAT_LIST_ACK [i]->read()));
289	TEST(Tcontrol_t,out_RETIRE_STAT_LIST_VAL [i]->read(),(in_RETIRE_VAL [i]->read() and
290	in_RETIRE_RAT_ACK [i]->read()));
291	}
292
293	SC_START(1);
294	}
295
296	/********************************************************
297	* Simulation - End
298	********************************************************/
299
300	TEST_OK ("End of Simulation");
301	delete _time;
302
303	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
304
305	delete in_CLOCK;
306	delete in_NRESET;
307
308	DELETE1_SC_SIGNAL( in_INSERT_RENAME_VAL ,_param->_nb_inst_insert);
309	DELETE1_SC_SIGNAL(out_INSERT_RENAME_ACK ,_param->_nb_inst_insert);
310	DELETE1_SC_SIGNAL(out_INSERT_INSERT_VAL ,_param->_nb_inst_insert);
311	DELETE1_SC_SIGNAL( in_INSERT_INSERT_ACK ,_param->_nb_inst_insert);
312	DELETE1_SC_SIGNAL(out_INSERT_RAT_INSERT_VAL ,_param->_nb_inst_insert);
313	DELETE1_SC_SIGNAL( in_INSERT_RAT_RENAME_ACK ,_param->_nb_inst_insert);
314	DELETE1_SC_SIGNAL( in_INSERT_RAT_INSERT_ACK ,_param->_nb_inst_insert);
315	DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_VAL ,_param->_nb_inst_insert);
316	DELETE1_SC_SIGNAL( in_INSERT_FREE_LIST_ACK ,_param->_nb_inst_insert);
317	DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_GPR_VAL ,_param->_nb_inst_insert);
318	DELETE1_SC_SIGNAL(out_INSERT_FREE_LIST_SPR_VAL ,_param->_nb_inst_insert);
319	DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_VAL ,_param->_nb_inst_insert);
320	DELETE1_SC_SIGNAL( in_INSERT_STAT_LIST_ACK ,_param->_nb_inst_insert);
321
322	DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RA ,_param->_nb_inst_insert);
323	DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RA_PHY ,_param->_nb_inst_insert);
324	DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RB ,_param->_nb_inst_insert);
325	DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RB_PHY ,_param->_nb_inst_insert);
326	DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_READ_RC ,_param->_nb_inst_insert);
327	DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RC_PHY ,_param->_nb_inst_insert);
328	DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_WRITE_RD ,_param->_nb_inst_insert);
329	DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_LOG ,_param->_nb_inst_insert);
330	DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_OLD,_param->_nb_inst_insert);
331	DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert);
332	DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_WRITE_RE ,_param->_nb_inst_insert);
333	DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_LOG ,_param->_nb_inst_insert);
334	DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_OLD,_param->_nb_inst_insert);
335	DELETE1_SC_SIGNAL( in_INSERT_DEPENDENCY_CHECKING_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert);
336
337	//DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RA ,_param->_nb_inst_insert);
338	//DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RA_PHY ,_param->_nb_inst_insert);
339	//DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RB ,_param->_nb_inst_insert);
340	//DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RB_PHY ,_param->_nb_inst_insert);
341	//DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_READ_RC ,_param->_nb_inst_insert);
342	//DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RC_PHY ,_param->_nb_inst_insert);
343	DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_WRITE_RD ,_param->_nb_inst_insert);
344	DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert);
345	DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert);
346	DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_WRITE_RE ,_param->_nb_inst_insert);
347	DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert);
348	DELETE1_SC_SIGNAL(out_INSERT_STAT_LIST_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert);
349
350	DELETE1_SC_SIGNAL(out_INSERT_RAT_WRITE_RD ,_param->_nb_inst_insert);
351	DELETE1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RD_LOG ,_param->_nb_inst_insert);
352	DELETE1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert);
353	DELETE1_SC_SIGNAL(out_INSERT_RAT_WRITE_RE ,_param->_nb_inst_insert);
354	DELETE1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RE_LOG ,_param->_nb_inst_insert);
355	DELETE1_SC_SIGNAL(out_INSERT_RAT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert);
356
357	DELETE1_SC_SIGNAL(out_INSERT_READ_RA ,_param->_nb_inst_insert);
358	DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert);
359	DELETE1_SC_SIGNAL(out_INSERT_READ_RB ,_param->_nb_inst_insert);
360	DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert);
361	DELETE1_SC_SIGNAL(out_INSERT_READ_RC ,_param->_nb_inst_insert);
362	DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert);
363	DELETE1_SC_SIGNAL(out_INSERT_WRITE_RD ,_param->_nb_inst_insert);
364	DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RD_LOG ,_param->_nb_inst_insert);
365	DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RD_PHY_OLD ,_param->_nb_inst_insert);
366	DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RD_PHY_NEW ,_param->_nb_inst_insert);
367	DELETE1_SC_SIGNAL(out_INSERT_WRITE_RE ,_param->_nb_inst_insert);
368	DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RE_LOG ,_param->_nb_inst_insert);
369	DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RE_PHY_OLD ,_param->_nb_inst_insert);
370	DELETE1_SC_SIGNAL(out_INSERT_NUM_REG_RE_PHY_NEW ,_param->_nb_inst_insert);
371
372	DELETE1_SC_SIGNAL( in_RETIRE_VAL ,_param->_nb_inst_retire);
373	DELETE1_SC_SIGNAL(out_RETIRE_ACK ,_param->_nb_inst_retire);
374	DELETE1_SC_SIGNAL(out_RETIRE_RAT_VAL ,_param->_nb_inst_retire);
375	DELETE1_SC_SIGNAL( in_RETIRE_RAT_ACK ,_param->_nb_inst_retire);
376	DELETE1_SC_SIGNAL(out_RETIRE_STAT_LIST_VAL,_param->_nb_inst_retire);
377	DELETE1_SC_SIGNAL( in_RETIRE_STAT_LIST_ACK,_param->_nb_inst_retire);
378
379	#endif
380
381	delete _Register_translation_unit_Glue;
382	#ifdef STATISTICS
383	delete _parameters_statistics;
384	#endif
385	}

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Register_translation_unit_Glue/SelfTest/src/test.cpp @ 117

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