[78] | 1 | /* |
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| 2 | * $Id$ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/SelfTest/include/test.h" |
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| 10 | #include "Common/include/Test.h" |
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| 11 | #include "Behavioural/include/Allocation.h" |
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| 12 | #include <list> |
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| 13 | |
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| 14 | #define NB_ITERATION 1 |
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| 15 | #define CYCLE_MAX (128*NB_ITERATION) |
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| 16 | |
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| 17 | #define LABEL(str...) \ |
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| 18 | { \ |
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| 19 | msg (_("{%d} "),static_cast<uint32_t>(sc_simulation_time())); \ |
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| 20 | msg (str); \ |
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| 21 | msg (_("\n")); \ |
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| 22 | } while(0) |
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| 23 | |
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| 24 | #define SC_START(cycle_offset) \ |
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| 25 | do \ |
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| 26 | { \ |
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| 27 | /*cout << "SC_START (begin)" << endl;*/ \ |
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| 28 | \ |
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| 29 | uint32_t cycle_current = static_cast<uint32_t>(sc_simulation_time()); \ |
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| 30 | if (cycle_offset != 0) \ |
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| 31 | { \ |
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| 32 | cout << "##########[ cycle "<< cycle_current+cycle_offset << " ]" << endl; \ |
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| 33 | } \ |
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| 34 | \ |
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| 35 | if (cycle_current > CYCLE_MAX) \ |
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| 36 | { \ |
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| 37 | TEST_KO("Maximal cycles Reached"); \ |
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| 38 | } \ |
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| 39 | \ |
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| 40 | sc_start(cycle_offset); \ |
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| 41 | \ |
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| 42 | /*cout << "SC_START (end )" << endl;*/ \ |
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| 43 | } while(0) |
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| 44 | |
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| 45 | |
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| 46 | class entry_t |
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| 47 | { |
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| 48 | public : bool _is_free ; |
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| 49 | public : bool _is_link ; |
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| 50 | public : bool _is_valid; |
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| 51 | public : uint32_t _counter ; |
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| 52 | }; |
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| 53 | |
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| 54 | |
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| 55 | void test (string name, |
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| 56 | morpheo::behavioural::core::multi_ooo_engine::ooo_engine::rename_unit::register_translation_unit::stat_list_unit::Parameters * _param) |
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| 57 | { |
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| 58 | msg(_("<%s> : Simulation SystemC.\n"),name.c_str()); |
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| 59 | |
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| 60 | #ifdef STATISTICS |
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| 61 | morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50); |
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| 62 | #endif |
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| 63 | |
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| 64 | Stat_List_unit * _Stat_List_unit = new Stat_List_unit (name.c_str(), |
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| 65 | #ifdef STATISTICS |
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| 66 | _parameters_statistics, |
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| 67 | #endif |
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| 68 | _param); |
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| 69 | |
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| 70 | #ifdef SYSTEMC |
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| 71 | /********************************************************************* |
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| 72 | * Déclarations des signaux |
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| 73 | *********************************************************************/ |
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| 74 | string rename; |
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| 75 | |
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| 76 | sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 77 | sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 78 | |
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| 79 | ALLOC1_SC_SIGNAL( in_INSERT_VAL ," in_INSERT_VAL ",Tcontrol_t ,_param->_nb_inst_insert); |
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| 80 | ALLOC1_SC_SIGNAL(out_INSERT_ACK ,"out_INSERT_ACK ",Tcontrol_t ,_param->_nb_inst_insert); |
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| 81 | ALLOC1_SC_SIGNAL( in_INSERT_READ_RA ," in_INSERT_READ_RA ",Tcontrol_t ,_param->_nb_inst_insert); |
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| 82 | ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RA_PHY ," in_INSERT_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_insert); |
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| 83 | ALLOC1_SC_SIGNAL( in_INSERT_READ_RB ," in_INSERT_READ_RB ",Tcontrol_t ,_param->_nb_inst_insert); |
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| 84 | ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RB_PHY ," in_INSERT_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_insert); |
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| 85 | ALLOC1_SC_SIGNAL( in_INSERT_READ_RC ," in_INSERT_READ_RC ",Tcontrol_t ,_param->_nb_inst_insert); |
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| 86 | ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RC_PHY ," in_INSERT_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_insert); |
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| 87 | ALLOC1_SC_SIGNAL( in_INSERT_WRITE_RD ," in_INSERT_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_insert); |
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| 88 | ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RD_PHY_NEW," in_INSERT_NUM_REG_RD_PHY_NEW",Tgeneral_address_t,_param->_nb_inst_insert); |
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| 89 | ALLOC1_SC_SIGNAL( in_INSERT_WRITE_RE ," in_INSERT_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_insert); |
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| 90 | ALLOC1_SC_SIGNAL( in_INSERT_NUM_REG_RE_PHY_NEW," in_INSERT_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_nb_inst_insert); |
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| 91 | ALLOC1_SC_SIGNAL( in_RETIRE_VAL ," in_RETIRE_VAL ",Tcontrol_t ,_param->_nb_inst_retire); |
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| 92 | ALLOC1_SC_SIGNAL(out_RETIRE_ACK ,"out_RETIRE_ACK ",Tcontrol_t ,_param->_nb_inst_retire); |
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| 93 | ALLOC1_SC_SIGNAL( in_RETIRE_READ_RA ," in_RETIRE_READ_RA ",Tcontrol_t ,_param->_nb_inst_retire); |
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| 94 | ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RA_PHY ," in_RETIRE_NUM_REG_RA_PHY ",Tgeneral_address_t,_param->_nb_inst_retire); |
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| 95 | ALLOC1_SC_SIGNAL( in_RETIRE_READ_RB ," in_RETIRE_READ_RB ",Tcontrol_t ,_param->_nb_inst_retire); |
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| 96 | ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RB_PHY ," in_RETIRE_NUM_REG_RB_PHY ",Tgeneral_address_t,_param->_nb_inst_retire); |
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| 97 | ALLOC1_SC_SIGNAL( in_RETIRE_READ_RC ," in_RETIRE_READ_RC ",Tcontrol_t ,_param->_nb_inst_retire); |
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| 98 | ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RC_PHY ," in_RETIRE_NUM_REG_RC_PHY ",Tspecial_address_t,_param->_nb_inst_retire); |
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| 99 | ALLOC1_SC_SIGNAL( in_RETIRE_WRITE_RD ," in_RETIRE_WRITE_RD ",Tcontrol_t ,_param->_nb_inst_retire); |
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| 100 | ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_OLD," in_RETIRE_NUM_REG_RD_PHY_OLD",Tgeneral_address_t,_param->_nb_inst_retire); |
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| 101 | ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RD_PHY_NEW," in_RETIRE_NUM_REG_RD_PHY_NEW",Tgeneral_address_t,_param->_nb_inst_retire); |
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| 102 | ALLOC1_SC_SIGNAL( in_RETIRE_WRITE_RE ," in_RETIRE_WRITE_RE ",Tcontrol_t ,_param->_nb_inst_retire); |
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| 103 | ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_OLD," in_RETIRE_NUM_REG_RE_PHY_OLD",Tspecial_address_t,_param->_nb_inst_retire); |
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| 104 | ALLOC1_SC_SIGNAL( in_RETIRE_NUM_REG_RE_PHY_NEW," in_RETIRE_NUM_REG_RE_PHY_NEW",Tspecial_address_t,_param->_nb_inst_retire); |
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| 105 | ALLOC1_SC_SIGNAL(out_PUSH_GPR_VAL ,"out_PUSH_GPR_VAL ",Tcontrol_t ,_param->_nb_reg_free); |
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| 106 | ALLOC1_SC_SIGNAL( in_PUSH_GPR_ACK ," in_PUSH_GPR_ACK ",Tcontrol_t ,_param->_nb_reg_free); |
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| 107 | ALLOC1_SC_SIGNAL(out_PUSH_GPR_NUM_REG ,"out_PUSH_GPR_NUM_REG ",Tgeneral_address_t,_param->_nb_reg_free); |
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| 108 | ALLOC1_SC_SIGNAL(out_PUSH_SPR_VAL ,"out_PUSH_SPR_VAL ",Tcontrol_t ,_param->_nb_reg_free); |
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| 109 | ALLOC1_SC_SIGNAL( in_PUSH_SPR_ACK ," in_PUSH_SPR_ACK ",Tcontrol_t ,_param->_nb_reg_free); |
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| 110 | ALLOC1_SC_SIGNAL(out_PUSH_SPR_NUM_REG ,"out_PUSH_SPR_NUM_REG ",Tspecial_address_t,_param->_nb_reg_free); |
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| 111 | |
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| 112 | |
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| 113 | /******************************************************** |
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| 114 | * Instanciation |
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| 115 | ********************************************************/ |
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| 116 | |
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| 117 | msg(_("<%s> : Instanciation of _Stat_List_unit.\n"),name.c_str()); |
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| 118 | |
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| 119 | (*(_Stat_List_unit->in_CLOCK)) (*(in_CLOCK)); |
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| 120 | (*(_Stat_List_unit->in_NRESET)) (*(in_NRESET)); |
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| 121 | |
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| 122 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_VAL ,_param->_nb_inst_insert); |
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| 123 | INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_INSERT_ACK ,_param->_nb_inst_insert); |
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| 124 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_READ_RA ,_param->_nb_inst_insert); |
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| 125 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RA_PHY ,_param->_nb_inst_insert); |
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| 126 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_READ_RB ,_param->_nb_inst_insert); |
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| 127 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RB_PHY ,_param->_nb_inst_insert); |
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| 128 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_READ_RC ,_param->_nb_inst_insert); |
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| 129 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RC_PHY ,_param->_nb_inst_insert); |
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| 130 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_WRITE_RD ,_param->_nb_inst_insert); |
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| 131 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RD_PHY_NEW,_param->_nb_inst_insert); |
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| 132 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_WRITE_RE ,_param->_nb_inst_insert); |
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| 133 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_INSERT_NUM_REG_RE_PHY_NEW,_param->_nb_inst_insert); |
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| 134 | |
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| 135 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_VAL ,_param->_nb_inst_retire); |
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| 136 | INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_RETIRE_ACK ,_param->_nb_inst_retire); |
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| 137 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_READ_RA ,_param->_nb_inst_retire); |
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| 138 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RA_PHY ,_param->_nb_inst_retire); |
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| 139 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_READ_RB ,_param->_nb_inst_retire); |
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| 140 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RB_PHY ,_param->_nb_inst_retire); |
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| 141 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_READ_RC ,_param->_nb_inst_retire); |
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| 142 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RC_PHY ,_param->_nb_inst_retire); |
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| 143 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_WRITE_RD ,_param->_nb_inst_retire); |
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| 144 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RD_PHY_OLD,_param->_nb_inst_retire); |
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| 145 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RD_PHY_NEW,_param->_nb_inst_retire); |
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| 146 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_WRITE_RE ,_param->_nb_inst_retire); |
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| 147 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RE_PHY_OLD,_param->_nb_inst_retire); |
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| 148 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_RETIRE_NUM_REG_RE_PHY_NEW,_param->_nb_inst_retire); |
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| 149 | |
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| 150 | INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_PUSH_GPR_VAL ,_param->_nb_reg_free); |
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| 151 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_PUSH_GPR_ACK ,_param->_nb_reg_free); |
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| 152 | INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_PUSH_GPR_NUM_REG ,_param->_nb_reg_free); |
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| 153 | |
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| 154 | INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_PUSH_SPR_VAL ,_param->_nb_reg_free); |
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| 155 | INSTANCE1_SC_SIGNAL(_Stat_List_unit, in_PUSH_SPR_ACK ,_param->_nb_reg_free); |
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| 156 | INSTANCE1_SC_SIGNAL(_Stat_List_unit,out_PUSH_SPR_NUM_REG ,_param->_nb_reg_free); |
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| 157 | |
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| 158 | msg(_("<%s> : Start Simulation ............\n"),name.c_str()); |
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| 159 | |
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| 160 | Time * _time = new Time(); |
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| 161 | |
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| 162 | /******************************************************** |
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| 163 | * Simulation - Begin |
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| 164 | ********************************************************/ |
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| 165 | |
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| 166 | // Initialisation |
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| 167 | |
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| 168 | const uint32_t seed = 0; |
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| 169 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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| 170 | |
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| 171 | srand(seed); |
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| 172 | |
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| 173 | int32_t percent_transaction_insert = 95; |
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| 174 | int32_t percent_transaction_retire = 95; |
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| 175 | int32_t percent_transaction_push = 95; |
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| 176 | |
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| 177 | uint32_t nb_thread = 0; |
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| 178 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 179 | nb_thread += _param->_nb_context [i]; |
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| 180 | |
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| 181 | SC_START(0); |
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| 182 | LABEL("Initialisation"); |
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| 183 | |
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| 184 | LABEL("Reset"); |
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| 185 | in_NRESET->write(0); |
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| 186 | SC_START(5); |
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| 187 | in_NRESET->write(1); |
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| 188 | |
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| 189 | LABEL("Loop of Test"); |
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| 190 | |
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| 191 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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| 192 | { |
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| 193 | LABEL("Iteration %d",iteration); |
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| 194 | |
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| 195 | entry_t gpr_status [_param->_nb_general_register]; |
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| 196 | entry_t spr_status [_param->_nb_special_register]; |
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| 197 | |
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| 198 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
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| 199 | { |
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| 200 | gpr_status[i]._is_free = false; |
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| 201 | gpr_status[i]._is_link = (i<(nb_thread*31+1)); |
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| 202 | gpr_status[i]._is_valid = true; |
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| 203 | gpr_status[i]._counter = 0; |
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| 204 | } |
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| 205 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
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| 206 | { |
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| 207 | spr_status[i]._is_free = false; |
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| 208 | spr_status[i]._is_link = (i<(nb_thread*2)); |
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| 209 | spr_status[i]._is_valid = true; |
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| 210 | spr_status[i]._counter = 0; |
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| 211 | } |
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| 212 | |
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| 213 | std::list<Tgeneral_address_t> free_list_gpr; |
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| 214 | std::list<Tgeneral_address_t> free_list_spr; |
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| 215 | |
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| 216 | // Test free register |
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| 217 | while ((free_list_gpr.size() < (_param->_nb_general_register - (nb_thread*31+1))) and |
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| 218 | (free_list_spr.size() < (_param->_nb_special_register - (nb_thread*2 )))) |
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| 219 | { |
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| 220 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
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| 221 | in_INSERT_VAL [i]->write(0); |
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| 222 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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| 223 | in_RETIRE_VAL [i]->write(0); |
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| 224 | |
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| 225 | for (uint32_t i=0; i<_param->_nb_reg_free; i++) |
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| 226 | { |
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| 227 | in_PUSH_GPR_ACK [i]->write((rand()%100)<percent_transaction_push); |
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| 228 | in_PUSH_SPR_ACK [i]->write((rand()%100)<percent_transaction_push); |
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| 229 | } |
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| 230 | |
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| 231 | SC_START(0); |
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| 232 | |
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| 233 | for (uint32_t i=0; i<_param->_nb_reg_free; i++) |
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| 234 | { |
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| 235 | if (out_PUSH_GPR_VAL [i]->read() and in_PUSH_GPR_ACK [i]->read()) |
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| 236 | { |
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| 237 | Tgeneral_address_t reg = out_PUSH_GPR_NUM_REG [i]->read(); |
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| 238 | |
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| 239 | LABEL("PUSH_GPR [%d] - Accepted",i); |
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| 240 | LABEL(" * reg : %d",reg); |
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| 241 | LABEL(" * status[%d]._is_free : %d",reg,spr_status[reg]._is_free ); |
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| 242 | LABEL(" * status[%d]._is_link : %d",reg,spr_status[reg]._is_link ); |
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| 243 | LABEL(" * status[%d]._is_valid : %d",reg,spr_status[reg]._is_valid); |
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| 244 | LABEL(" * status[%d]._counter : %d",reg,spr_status[reg]._counter ); |
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| 245 | |
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| 246 | TEST(bool, true,((gpr_status[reg]._is_free == 0) and |
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| 247 | (gpr_status[reg]._is_link == 0) and |
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| 248 | (gpr_status[reg]._is_valid == 1) and |
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| 249 | (gpr_status[reg]._counter == 0))); |
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| 250 | |
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| 251 | gpr_status[reg]._is_free = 1; |
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| 252 | free_list_gpr.push_back(reg); |
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| 253 | } |
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| 254 | |
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| 255 | if (out_PUSH_SPR_VAL [i]->read() and in_PUSH_SPR_ACK [i]->read()) |
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| 256 | { |
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| 257 | Tspecial_address_t reg = out_PUSH_SPR_NUM_REG [i]->read(); |
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| 258 | |
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| 259 | LABEL("PUSH_SPR [%d] - Accepted",i); |
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| 260 | LABEL(" * reg : %d",reg); |
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| 261 | LABEL(" * status[%d]._is_free : %d",reg,spr_status[reg]._is_free ); |
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| 262 | LABEL(" * status[%d]._is_link : %d",reg,spr_status[reg]._is_link ); |
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| 263 | LABEL(" * status[%d]._is_valid : %d",reg,spr_status[reg]._is_valid); |
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| 264 | LABEL(" * status[%d]._counter : %d",reg,spr_status[reg]._counter ); |
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| 265 | |
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| 266 | TEST(bool, true,((spr_status[reg]._is_free == 0) and |
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| 267 | (spr_status[reg]._is_link == 0) and |
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| 268 | (spr_status[reg]._is_valid == 1) and |
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| 269 | (spr_status[reg]._counter == 0))); |
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| 270 | |
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| 271 | spr_status[reg]._is_free = 1; |
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| 272 | free_list_spr.push_back(reg); |
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| 273 | } |
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| 274 | } |
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| 275 | |
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| 276 | SC_START(1); |
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| 277 | } |
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| 278 | |
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| 279 | LABEL("======================="); |
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| 280 | LABEL("===== END OF INIT ====="); |
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| 281 | LABEL("======================="); |
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| 282 | |
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| 283 | int32_t nb_cycle = 64; |
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| 284 | |
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| 285 | while (nb_cycle > 0) |
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| 286 | { |
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| 287 | std::list<Tgeneral_address_t>::iterator it_gpr = free_list_gpr.begin(); |
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| 288 | std::list<Tspecial_address_t>::iterator it_spr = free_list_spr.begin(); |
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| 289 | |
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| 290 | |
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| 291 | entry_t gpr_status_insert [_param->_nb_general_register]; |
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| 292 | entry_t spr_status_insert [_param->_nb_special_register]; |
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| 293 | entry_t gpr_status_retire [_param->_nb_general_register]; |
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| 294 | entry_t spr_status_retire [_param->_nb_special_register]; |
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| 295 | |
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| 296 | for (uint32_t i=0; i<_param->_nb_general_register; i++) |
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| 297 | { |
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| 298 | gpr_status_insert [i] = gpr_status[i]; |
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| 299 | gpr_status_retire [i] = gpr_status[i]; |
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| 300 | } |
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| 301 | for (uint32_t i=0; i<_param->_nb_special_register; i++) |
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| 302 | { |
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| 303 | spr_status_insert [i] = spr_status[i]; |
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| 304 | spr_status_retire [i] = spr_status[i]; |
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| 305 | } |
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| 306 | |
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| 307 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
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| 308 | { |
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| 309 | Tgeneral_address_t ra = (rand()%(_param->_nb_general_register-1))+1; |
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| 310 | Tgeneral_address_t rb = (rand()%(_param->_nb_general_register-1))+1; |
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| 311 | Tspecial_address_t rc = (rand()%(_param->_nb_special_register )) ; |
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| 312 | Tgeneral_address_t rd = (it_gpr != free_list_gpr.end())?*it_gpr:0; |
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| 313 | Tspecial_address_t re = (it_spr != free_list_spr.end())?*it_spr:0; |
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| 314 | |
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| 315 | Tcontrol_t read_ra = (gpr_status_insert[ra]._is_link) and (gpr_status_insert[ra]._counter < _param->_max_reader); |
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| 316 | Tcontrol_t read_rb = (gpr_status_insert[rb]._is_link) and (gpr_status_insert[rb]._counter < _param->_max_reader); |
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| 317 | Tcontrol_t read_rc = (spr_status_insert[rc]._is_link) and (spr_status_insert[rc]._counter < _param->_max_reader); |
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| 318 | Tcontrol_t write_rd = (it_gpr != free_list_gpr.end()); |
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| 319 | Tcontrol_t write_re = (it_spr != free_list_spr.end()); |
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| 320 | |
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| 321 | in_INSERT_VAL [i]->write((rand()%100) < percent_transaction_insert); |
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| 322 | in_INSERT_READ_RA [i]->write(read_ra ); |
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| 323 | in_INSERT_NUM_REG_RA_PHY [i]->write(ra); |
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| 324 | in_INSERT_READ_RB [i]->write(read_rb ); |
---|
| 325 | in_INSERT_NUM_REG_RB_PHY [i]->write(rb); |
---|
| 326 | in_INSERT_READ_RC [i]->write(read_rc ); |
---|
| 327 | in_INSERT_NUM_REG_RC_PHY [i]->write(rc); |
---|
| 328 | in_INSERT_WRITE_RD [i]->write(write_rd); |
---|
| 329 | in_INSERT_NUM_REG_RD_PHY_NEW [i]->write(rd); |
---|
| 330 | in_INSERT_WRITE_RE [i]->write(write_re); |
---|
| 331 | in_INSERT_NUM_REG_RE_PHY_NEW [i]->write(re); |
---|
| 332 | |
---|
| 333 | if (read_ra) |
---|
| 334 | gpr_status_insert[ra]._counter++; |
---|
| 335 | if (read_rb) |
---|
| 336 | gpr_status_insert[rb]._counter++; |
---|
| 337 | if (read_rc) |
---|
| 338 | spr_status_insert[rc]._counter++; |
---|
| 339 | if (write_rd) |
---|
| 340 | it_gpr ++; |
---|
| 341 | if (write_re) |
---|
| 342 | it_spr ++; |
---|
| 343 | } |
---|
| 344 | |
---|
| 345 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
---|
| 346 | { |
---|
| 347 | Tgeneral_address_t ra = (rand()%(_param->_nb_general_register-1))+1; |
---|
| 348 | Tgeneral_address_t rb = (rand()%(_param->_nb_general_register-1))+1; |
---|
| 349 | Tspecial_address_t rc = (rand()%(_param->_nb_special_register )) ; |
---|
| 350 | Tgeneral_address_t rd_old = (rand()%(_param->_nb_general_register-1))+1; |
---|
| 351 | Tgeneral_address_t rd_new = (rand()%(_param->_nb_general_register-1))+1; |
---|
| 352 | Tspecial_address_t re_old = (rand()%(_param->_nb_special_register )) ; |
---|
| 353 | Tspecial_address_t re_new = (rand()%(_param->_nb_special_register )) ; |
---|
| 354 | |
---|
| 355 | Tcontrol_t read_ra = (gpr_status_retire[ra]._is_link) and (gpr_status_retire[ra]._counter > 0); |
---|
| 356 | Tcontrol_t read_rb = (gpr_status_retire[rb]._is_link) and (gpr_status_retire[rb]._counter > 0); |
---|
| 357 | Tcontrol_t read_rc = (spr_status_retire[rc]._is_link) and (spr_status_retire[rc]._counter > 0); |
---|
| 358 | Tcontrol_t write_rd = ( (gpr_status_retire[rd_old]._is_link ) and |
---|
| 359 | (gpr_status_retire[rd_old]._is_valid) and |
---|
| 360 | (gpr_status_retire[rd_new]._is_link ) and |
---|
| 361 | not (gpr_status_retire[rd_new]._is_valid)); |
---|
| 362 | Tcontrol_t write_re = ( (spr_status_retire[re_old]._is_link ) and |
---|
| 363 | (spr_status_retire[re_old]._is_valid) and |
---|
| 364 | (spr_status_retire[re_new]._is_link ) and |
---|
| 365 | not (spr_status_retire[re_new]._is_valid)); |
---|
| 366 | |
---|
| 367 | in_RETIRE_VAL [i]->write((rand()%100) < percent_transaction_retire); |
---|
| 368 | in_RETIRE_READ_RA [i]->write(read_ra ); |
---|
| 369 | in_RETIRE_NUM_REG_RA_PHY [i]->write(ra); |
---|
| 370 | in_RETIRE_READ_RB [i]->write(read_rb ); |
---|
| 371 | in_RETIRE_NUM_REG_RB_PHY [i]->write(rb); |
---|
| 372 | in_RETIRE_READ_RC [i]->write(read_rc ); |
---|
| 373 | in_RETIRE_NUM_REG_RC_PHY [i]->write(rc); |
---|
| 374 | in_RETIRE_WRITE_RD [i]->write(write_rd); |
---|
| 375 | in_RETIRE_NUM_REG_RD_PHY_OLD [i]->write(rd_old); |
---|
| 376 | in_RETIRE_NUM_REG_RD_PHY_NEW [i]->write(rd_new); |
---|
| 377 | in_RETIRE_WRITE_RE [i]->write(write_re); |
---|
| 378 | in_RETIRE_NUM_REG_RE_PHY_OLD [i]->write(re_old); |
---|
| 379 | in_RETIRE_NUM_REG_RE_PHY_NEW [i]->write(re_new); |
---|
| 380 | |
---|
| 381 | if (read_ra) |
---|
| 382 | { |
---|
| 383 | gpr_status_retire[ra]._counter --; |
---|
| 384 | } |
---|
| 385 | if (read_rb) |
---|
| 386 | { |
---|
| 387 | gpr_status_retire[rb]._counter --; |
---|
| 388 | } |
---|
| 389 | if (read_rc) |
---|
| 390 | { |
---|
| 391 | spr_status_retire[rc]._counter --; |
---|
| 392 | } |
---|
| 393 | if (write_rd) |
---|
| 394 | { |
---|
| 395 | gpr_status_retire[rd_old]._is_link = 0; |
---|
| 396 | gpr_status_retire[rd_new]._is_valid = 1; |
---|
| 397 | } |
---|
| 398 | if (write_re) |
---|
| 399 | { |
---|
| 400 | spr_status_retire[re_old]._is_link = 0; |
---|
| 401 | spr_status_retire[re_new]._is_valid = 1; |
---|
| 402 | } |
---|
| 403 | |
---|
| 404 | } |
---|
| 405 | |
---|
| 406 | |
---|
| 407 | for (uint32_t i=0; i<_param->_nb_reg_free; i++) |
---|
| 408 | { |
---|
| 409 | in_PUSH_GPR_ACK [i]->write((rand()%100)<percent_transaction_push); |
---|
| 410 | in_PUSH_SPR_ACK [i]->write((rand()%100)<percent_transaction_push); |
---|
| 411 | } |
---|
| 412 | |
---|
| 413 | SC_START(0); |
---|
| 414 | |
---|
| 415 | it_gpr = free_list_gpr.begin(); |
---|
| 416 | it_spr = free_list_spr.begin(); |
---|
| 417 | |
---|
| 418 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
---|
| 419 | { |
---|
| 420 | Tcontrol_t write_rd = in_INSERT_WRITE_RD [i]->read(); |
---|
| 421 | Tcontrol_t write_re = in_INSERT_WRITE_RE [i]->read(); |
---|
| 422 | |
---|
| 423 | if (in_INSERT_VAL [i]->read() and out_INSERT_ACK [i]->read()) |
---|
| 424 | { |
---|
| 425 | Tcontrol_t read_ra = in_INSERT_READ_RA [i]->read(); |
---|
| 426 | Tgeneral_address_t ra = in_INSERT_NUM_REG_RA_PHY [i]->read(); |
---|
| 427 | Tcontrol_t read_rb = in_INSERT_READ_RB [i]->read(); |
---|
| 428 | Tgeneral_address_t rb = in_INSERT_NUM_REG_RB_PHY [i]->read(); |
---|
| 429 | Tcontrol_t read_rc = in_INSERT_READ_RC [i]->read(); |
---|
| 430 | Tspecial_address_t rc = in_INSERT_NUM_REG_RC_PHY [i]->read(); |
---|
| 431 | Tgeneral_address_t rd_new = in_INSERT_NUM_REG_RD_PHY_NEW [i]->read(); |
---|
| 432 | Tspecial_address_t re_new = in_INSERT_NUM_REG_RE_PHY_NEW [i]->read(); |
---|
| 433 | |
---|
| 434 | LABEL("INSERT [%d] - Accepted",i); |
---|
| 435 | LABEL(" * read_ra : %d",read_ra ); |
---|
| 436 | LABEL(" * reg_ra : %d",ra ); |
---|
| 437 | LABEL(" * status[%d]._is_free : %d",ra,spr_status[ra]._is_free ); |
---|
| 438 | LABEL(" * status[%d]._is_link : %d",ra,spr_status[ra]._is_link ); |
---|
| 439 | LABEL(" * status[%d]._is_valid : %d",ra,spr_status[ra]._is_valid); |
---|
| 440 | LABEL(" * status[%d]._counter : %d",ra,spr_status[ra]._counter ); |
---|
| 441 | LABEL(" * read_rb : %d",read_rb ); |
---|
| 442 | LABEL(" * reg_rb : %d",rb ); |
---|
| 443 | LABEL(" * status[%d]._is_free : %d",rb,spr_status[rb]._is_free ); |
---|
| 444 | LABEL(" * status[%d]._is_link : %d",rb,spr_status[rb]._is_link ); |
---|
| 445 | LABEL(" * status[%d]._is_valid : %d",rb,spr_status[rb]._is_valid); |
---|
| 446 | LABEL(" * status[%d]._counter : %d",rb,spr_status[rb]._counter ); |
---|
| 447 | LABEL(" * read_rc : %d",read_rc ); |
---|
| 448 | LABEL(" * reg_rc : %d",rc ); |
---|
| 449 | LABEL(" * status[%d]._is_free : %d",rc,spr_status[rc]._is_free ); |
---|
| 450 | LABEL(" * status[%d]._is_link : %d",rc,spr_status[rc]._is_link ); |
---|
| 451 | LABEL(" * status[%d]._is_valid : %d",rc,spr_status[rc]._is_valid); |
---|
| 452 | LABEL(" * status[%d]._counter : %d",rc,spr_status[rc]._counter ); |
---|
| 453 | LABEL(" * read_rd : %d",write_rd); |
---|
| 454 | LABEL(" * reg_rd_new : %d",rd_new ); |
---|
| 455 | LABEL(" * status[%d]._is_free : %d",rd_new,spr_status[rd_new]._is_free ); |
---|
| 456 | LABEL(" * status[%d]._is_link : %d",rd_new,spr_status[rd_new]._is_link ); |
---|
| 457 | LABEL(" * status[%d]._is_valid : %d",rd_new,spr_status[rd_new]._is_valid); |
---|
| 458 | LABEL(" * status[%d]._counter : %d",rd_new,spr_status[rd_new]._counter ); |
---|
| 459 | LABEL(" * read_re : %d",write_re); |
---|
| 460 | LABEL(" * reg_re_new : %d",re_new ); |
---|
| 461 | LABEL(" * status[%d]._is_free : %d",re_new,spr_status[re_new]._is_free ); |
---|
| 462 | LABEL(" * status[%d]._is_link : %d",re_new,spr_status[re_new]._is_link ); |
---|
| 463 | LABEL(" * status[%d]._is_valid : %d",re_new,spr_status[re_new]._is_valid); |
---|
| 464 | LABEL(" * status[%d]._counter : %d",re_new,spr_status[re_new]._counter ); |
---|
| 465 | |
---|
| 466 | if (read_ra) |
---|
| 467 | { |
---|
| 468 | gpr_status[ra]._counter ++; |
---|
| 469 | } |
---|
| 470 | if (read_rb) |
---|
| 471 | { |
---|
| 472 | gpr_status[rb]._counter ++; |
---|
| 473 | } |
---|
| 474 | if (read_rc) |
---|
| 475 | { |
---|
| 476 | spr_status[rc]._counter ++; |
---|
| 477 | } |
---|
| 478 | if (write_rd) |
---|
| 479 | { |
---|
| 480 | Tgeneral_address_t reg = *it_gpr; |
---|
| 481 | TEST(Tgeneral_address_t,reg,rd_new); |
---|
| 482 | |
---|
| 483 | it_gpr = free_list_gpr.erase(it_gpr); |
---|
| 484 | |
---|
| 485 | gpr_status[reg]._is_free = 0; |
---|
| 486 | gpr_status[reg]._is_link = 1; |
---|
| 487 | gpr_status[reg]._is_valid = 0; |
---|
| 488 | } |
---|
| 489 | |
---|
| 490 | if (write_re) |
---|
| 491 | { |
---|
| 492 | Tspecial_address_t reg = *it_spr; |
---|
| 493 | TEST(Tspecial_address_t,reg,re_new); |
---|
| 494 | |
---|
| 495 | it_spr = free_list_spr.erase(it_spr); |
---|
| 496 | |
---|
| 497 | spr_status[reg]._is_free = 0; |
---|
| 498 | spr_status[reg]._is_link = 1; |
---|
| 499 | spr_status[reg]._is_valid = 0; |
---|
| 500 | } |
---|
| 501 | } |
---|
| 502 | else |
---|
| 503 | { |
---|
| 504 | if (write_rd) |
---|
| 505 | it_gpr ++; |
---|
| 506 | if (write_re) |
---|
| 507 | it_spr ++; |
---|
| 508 | } |
---|
| 509 | } |
---|
| 510 | |
---|
| 511 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
---|
| 512 | if (in_RETIRE_VAL [i]->read() and out_RETIRE_ACK [i]->read()) |
---|
| 513 | { |
---|
| 514 | Tcontrol_t read_ra = in_RETIRE_READ_RA [i]->read(); |
---|
| 515 | Tgeneral_address_t ra = in_RETIRE_NUM_REG_RA_PHY [i]->read(); |
---|
| 516 | Tcontrol_t read_rb = in_RETIRE_READ_RB [i]->read(); |
---|
| 517 | Tgeneral_address_t rb = in_RETIRE_NUM_REG_RB_PHY [i]->read(); |
---|
| 518 | Tcontrol_t read_rc = in_RETIRE_READ_RC [i]->read(); |
---|
| 519 | Tspecial_address_t rc = in_RETIRE_NUM_REG_RC_PHY [i]->read(); |
---|
| 520 | Tcontrol_t write_rd = in_RETIRE_WRITE_RD [i]->read(); |
---|
| 521 | Tgeneral_address_t rd_old = in_RETIRE_NUM_REG_RD_PHY_OLD [i]->read(); |
---|
| 522 | Tgeneral_address_t rd_new = in_RETIRE_NUM_REG_RD_PHY_NEW [i]->read(); |
---|
| 523 | Tcontrol_t write_re = in_RETIRE_WRITE_RE [i]->read(); |
---|
| 524 | Tgeneral_address_t re_old = in_RETIRE_NUM_REG_RE_PHY_OLD [i]->read(); |
---|
| 525 | Tgeneral_address_t re_new = in_RETIRE_NUM_REG_RE_PHY_NEW [i]->read(); |
---|
| 526 | |
---|
| 527 | LABEL("RETIRE [%d] - Accepted",i); |
---|
| 528 | LABEL(" * read_ra : %d",read_ra ); |
---|
| 529 | LABEL(" * reg_ra : %d",ra ); |
---|
| 530 | LABEL(" * status[%d]._is_free : %d",ra,spr_status[ra]._is_free ); |
---|
| 531 | LABEL(" * status[%d]._is_link : %d",ra,spr_status[ra]._is_link ); |
---|
| 532 | LABEL(" * status[%d]._is_valid : %d",ra,spr_status[ra]._is_valid); |
---|
| 533 | LABEL(" * status[%d]._counter : %d",ra,spr_status[ra]._counter ); |
---|
| 534 | LABEL(" * read_rb : %d",read_rb ); |
---|
| 535 | LABEL(" * reg_rb : %d",rb ); |
---|
| 536 | LABEL(" * status[%d]._is_free : %d",rb,spr_status[rb]._is_free ); |
---|
| 537 | LABEL(" * status[%d]._is_link : %d",rb,spr_status[rb]._is_link ); |
---|
| 538 | LABEL(" * status[%d]._is_valid : %d",rb,spr_status[rb]._is_valid); |
---|
| 539 | LABEL(" * status[%d]._counter : %d",rb,spr_status[rb]._counter ); |
---|
| 540 | LABEL(" * read_rc : %d",read_rc ); |
---|
| 541 | LABEL(" * reg_rc : %d",rc ); |
---|
| 542 | LABEL(" * status[%d]._is_free : %d",rc,spr_status[rc]._is_free ); |
---|
| 543 | LABEL(" * status[%d]._is_link : %d",rc,spr_status[rc]._is_link ); |
---|
| 544 | LABEL(" * status[%d]._is_valid : %d",rc,spr_status[rc]._is_valid); |
---|
| 545 | LABEL(" * status[%d]._counter : %d",rc,spr_status[rc]._counter ); |
---|
| 546 | LABEL(" * read_rd : %d",write_rd); |
---|
| 547 | LABEL(" * reg_rd_old : %d",rd_old ); |
---|
| 548 | LABEL(" * status[%d]._is_free : %d",rd_old,spr_status[rd_old]._is_free ); |
---|
| 549 | LABEL(" * status[%d]._is_link : %d",rd_old,spr_status[rd_old]._is_link ); |
---|
| 550 | LABEL(" * status[%d]._is_valid : %d",rd_old,spr_status[rd_old]._is_valid); |
---|
| 551 | LABEL(" * status[%d]._counter : %d",rd_old,spr_status[rd_old]._counter ); |
---|
| 552 | LABEL(" * reg_rd_new : %d",rd_new ); |
---|
| 553 | LABEL(" * status[%d]._is_free : %d",rd_new,spr_status[rd_new]._is_free ); |
---|
| 554 | LABEL(" * status[%d]._is_link : %d",rd_new,spr_status[rd_new]._is_link ); |
---|
| 555 | LABEL(" * status[%d]._is_valid : %d",rd_new,spr_status[rd_new]._is_valid); |
---|
| 556 | LABEL(" * status[%d]._counter : %d",rd_new,spr_status[rd_new]._counter ); |
---|
| 557 | LABEL(" * read_re : %d",write_re); |
---|
| 558 | LABEL(" * reg_re_old : %d",re_old ); |
---|
| 559 | LABEL(" * status[%d]._is_free : %d",re_old,spr_status[re_old]._is_free ); |
---|
| 560 | LABEL(" * status[%d]._is_link : %d",re_old,spr_status[re_old]._is_link ); |
---|
| 561 | LABEL(" * status[%d]._is_valid : %d",re_old,spr_status[re_old]._is_valid); |
---|
| 562 | LABEL(" * status[%d]._counter : %d",re_old,spr_status[re_old]._counter ); |
---|
| 563 | LABEL(" * reg_re_new : %d",re_new ); |
---|
| 564 | LABEL(" * status[%d]._is_free : %d",re_new,spr_status[re_new]._is_free ); |
---|
| 565 | LABEL(" * status[%d]._is_link : %d",re_new,spr_status[re_new]._is_link ); |
---|
| 566 | LABEL(" * status[%d]._is_valid : %d",re_new,spr_status[re_new]._is_valid); |
---|
| 567 | LABEL(" * status[%d]._counter : %d",re_new,spr_status[re_new]._counter ); |
---|
| 568 | |
---|
| 569 | if (read_ra) |
---|
| 570 | { |
---|
| 571 | gpr_status[ra]._counter --; |
---|
| 572 | } |
---|
| 573 | if (read_rb) |
---|
| 574 | { |
---|
| 575 | gpr_status[rb]._counter --; |
---|
| 576 | } |
---|
| 577 | if (read_rc) |
---|
| 578 | { |
---|
| 579 | spr_status[rc]._counter --; |
---|
| 580 | } |
---|
| 581 | if (write_rd) |
---|
| 582 | { |
---|
| 583 | gpr_status[rd_old]._is_link = 0; |
---|
| 584 | gpr_status[rd_new]._is_valid = 1; |
---|
| 585 | } |
---|
| 586 | if (write_re) |
---|
| 587 | { |
---|
| 588 | spr_status[re_old]._is_link = 0; |
---|
| 589 | spr_status[re_new]._is_valid = 1; |
---|
| 590 | } |
---|
| 591 | } |
---|
| 592 | |
---|
| 593 | |
---|
| 594 | for (uint32_t i=0; i<_param->_nb_reg_free; i++) |
---|
| 595 | { |
---|
| 596 | if (out_PUSH_GPR_VAL [i]->read() and in_PUSH_GPR_ACK [i]->read()) |
---|
| 597 | { |
---|
| 598 | Tgeneral_address_t reg = out_PUSH_GPR_NUM_REG [i]->read(); |
---|
| 599 | |
---|
| 600 | LABEL("PUSH_GPR [%d] - Accepted",i); |
---|
| 601 | LABEL(" * reg : %d",reg); |
---|
| 602 | LABEL(" * status[%d]._is_free : %d",reg,spr_status[reg]._is_free ); |
---|
| 603 | LABEL(" * status[%d]._is_link : %d",reg,spr_status[reg]._is_link ); |
---|
| 604 | LABEL(" * status[%d]._is_valid : %d",reg,spr_status[reg]._is_valid); |
---|
| 605 | LABEL(" * status[%d]._counter : %d",reg,spr_status[reg]._counter ); |
---|
| 606 | |
---|
| 607 | TEST(bool, true,((gpr_status[reg]._is_free == 0) and |
---|
| 608 | (gpr_status[reg]._is_link == 0) and |
---|
| 609 | (gpr_status[reg]._is_valid == 1) and |
---|
| 610 | (gpr_status[reg]._counter == 0))); |
---|
| 611 | |
---|
| 612 | gpr_status[reg]._is_free = 1; |
---|
| 613 | free_list_gpr.push_back(reg); |
---|
| 614 | } |
---|
| 615 | |
---|
| 616 | if (out_PUSH_SPR_VAL [i]->read() and in_PUSH_SPR_ACK [i]->read()) |
---|
| 617 | { |
---|
| 618 | Tspecial_address_t reg = out_PUSH_SPR_NUM_REG [i]->read(); |
---|
| 619 | |
---|
| 620 | LABEL("PUSH_SPR [%d] - Accepted",i); |
---|
| 621 | LABEL(" * reg : %d",reg); |
---|
| 622 | LABEL(" * status[%d]._is_free : %d",reg,spr_status[reg]._is_free ); |
---|
| 623 | LABEL(" * status[%d]._is_link : %d",reg,spr_status[reg]._is_link ); |
---|
| 624 | LABEL(" * status[%d]._is_valid : %d",reg,spr_status[reg]._is_valid); |
---|
| 625 | LABEL(" * status[%d]._counter : %d",reg,spr_status[reg]._counter ); |
---|
| 626 | |
---|
| 627 | TEST(bool, true,((spr_status[reg]._is_free == 0) and |
---|
| 628 | (spr_status[reg]._is_link == 0) and |
---|
| 629 | (spr_status[reg]._is_valid == 1) and |
---|
| 630 | (spr_status[reg]._counter == 0))); |
---|
| 631 | |
---|
| 632 | spr_status[reg]._is_free = 1; |
---|
| 633 | free_list_spr.push_back(reg); |
---|
| 634 | } |
---|
| 635 | } |
---|
| 636 | |
---|
| 637 | SC_START(1); |
---|
| 638 | nb_cycle --; |
---|
| 639 | } |
---|
| 640 | } |
---|
| 641 | |
---|
| 642 | /******************************************************** |
---|
| 643 | * Simulation - End |
---|
| 644 | ********************************************************/ |
---|
| 645 | |
---|
| 646 | TEST_OK ("End of Simulation"); |
---|
| 647 | delete _time; |
---|
| 648 | |
---|
| 649 | msg(_("<%s> : ............ Stop Simulation\n"),name.c_str()); |
---|
| 650 | |
---|
| 651 | delete in_CLOCK; |
---|
| 652 | delete in_NRESET; |
---|
| 653 | |
---|
| 654 | delete [] in_INSERT_VAL ; |
---|
| 655 | delete [] out_INSERT_ACK ; |
---|
| 656 | delete [] in_INSERT_READ_RA ; |
---|
| 657 | delete [] in_INSERT_NUM_REG_RA_PHY ; |
---|
| 658 | delete [] in_INSERT_READ_RB ; |
---|
| 659 | delete [] in_INSERT_NUM_REG_RB_PHY ; |
---|
| 660 | delete [] in_INSERT_READ_RC ; |
---|
| 661 | delete [] in_INSERT_NUM_REG_RC_PHY ; |
---|
| 662 | delete [] in_INSERT_WRITE_RD ; |
---|
| 663 | delete [] in_INSERT_NUM_REG_RD_PHY_NEW; |
---|
| 664 | delete [] in_INSERT_WRITE_RE ; |
---|
| 665 | delete [] in_INSERT_NUM_REG_RE_PHY_NEW; |
---|
| 666 | delete [] in_RETIRE_VAL ; |
---|
| 667 | delete [] out_RETIRE_ACK ; |
---|
| 668 | delete [] in_RETIRE_READ_RA ; |
---|
| 669 | delete [] in_RETIRE_NUM_REG_RA_PHY ; |
---|
| 670 | delete [] in_RETIRE_READ_RB ; |
---|
| 671 | delete [] in_RETIRE_NUM_REG_RB_PHY ; |
---|
| 672 | delete [] in_RETIRE_READ_RC ; |
---|
| 673 | delete [] in_RETIRE_NUM_REG_RC_PHY ; |
---|
| 674 | delete [] in_RETIRE_WRITE_RD ; |
---|
| 675 | delete [] in_RETIRE_NUM_REG_RD_PHY_OLD; |
---|
| 676 | delete [] in_RETIRE_NUM_REG_RD_PHY_NEW; |
---|
| 677 | delete [] in_RETIRE_WRITE_RE ; |
---|
| 678 | delete [] in_RETIRE_NUM_REG_RE_PHY_OLD; |
---|
| 679 | delete [] in_RETIRE_NUM_REG_RE_PHY_NEW; |
---|
| 680 | delete [] out_PUSH_GPR_VAL ; |
---|
| 681 | delete [] in_PUSH_GPR_ACK ; |
---|
| 682 | delete [] out_PUSH_GPR_NUM_REG ; |
---|
| 683 | delete [] out_PUSH_SPR_VAL ; |
---|
| 684 | delete [] in_PUSH_SPR_ACK ; |
---|
| 685 | delete [] out_PUSH_SPR_NUM_REG ; |
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| 686 | |
---|
| 687 | #endif |
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| 688 | |
---|
| 689 | delete _Stat_List_unit; |
---|
| 690 | #ifdef STATISTICS |
---|
| 691 | delete _parameters_statistics; |
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| 692 | #endif |
---|
| 693 | } |
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