source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/src/Stat_List_unit_genMealy.cpp @ 112

Last change on this file since 112 was 112, checked in by rosiere, 15 years ago

1) Stat_list : fix retire old and new register bug
2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step)
3) Model : add class Model (cf Morpheo.sim)
4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array.
5) Script : add distexe.sh
6) Add Comparator, Multiplier, Divider. But this component are not implemented
7) Software : add Dhrystone

  • Property svn:keywords set to Id
File size: 2.1 KB
Line 
1#ifdef SYSTEMC
2/*
3 * $Id: Stat_List_unit_genMealy.cpp 112 2009-03-18 22:36:26Z rosiere $
4 *
5 * [ Description ]
6 *
7 */
8
9#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_ooo_engine {
15namespace ooo_engine {
16namespace rename_unit {
17namespace register_translation_unit {
18namespace stat_list_unit {
19
20
21// #undef  FUNCTION
22// #define FUNCTION "Stat_List_unit::genMealy"
23//   void Stat_List_unit::genMealy (void)
24//   {
25//     log_begin(Stat_List_unit,FUNCTION);
26//     log_function(Stat_List_unit,FUNCTION,_name.c_str());
27
28//     for (uint32_t i=0; i<_param->_nb_inst_insert; i++)
29//       {
30//      bool ack = true;
31
32//      if (PORT_READ(in_INSERT_READ_RA [i]))
33//        {
34//          Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]);
35//          uint32_t bank = num_reg >> _param->_shift_gpr;
36//          uint32_t reg  = num_reg  & _param->_mask_gpr ;
37//          ack &= gpr_stat_list [bank][reg].can_insert_read(_param->_max_reader);
38//        }
39
40//      if (PORT_READ(in_INSERT_READ_RB [i]))
41//        {
42//          Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]);
43//          uint32_t bank = num_reg >> _param->_shift_gpr;
44//          uint32_t reg  = num_reg  & _param->_mask_gpr ;
45//          ack &= gpr_stat_list [bank][reg].can_insert_read(_param->_max_reader);
46//        }
47
48//      if (PORT_READ(in_INSERT_READ_RC [i]))
49//        {
50//          Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]);
51//          uint32_t bank = num_reg >> _param->_shift_spr;
52//          uint32_t reg  = num_reg  & _param->_mask_spr ;
53//          ack &= spr_stat_list [bank][reg].can_insert_read(_param->_max_reader);
54//        }
55
56//      internal_INSERT_ACK [i] = ack;
57//      PORT_WRITE(out_INSERT_ACK [i], ack);
58//       }
59   
60//     log_end(Stat_List_unit,FUNCTION);
61//   };
62
63}; // end namespace stat_list_unit
64}; // end namespace register_translation_unit
65}; // end namespace rename_unit
66}; // end namespace ooo_engine
67}; // end namespace multi_ooo_engine
68}; // end namespace core
69
70}; // end namespace behavioural
71}; // end namespace morpheo             
72#endif
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