1 | #ifdef SYSTEMC |
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2 | /* |
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3 | * $Id: Stat_List_unit_transition.cpp 81 2008-04-15 18:40:01Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Rename_unit/Register_translation_unit/Stat_List_unit/include/Stat_List_unit.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace core { |
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14 | namespace multi_ooo_engine { |
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15 | namespace ooo_engine { |
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16 | namespace rename_unit { |
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17 | namespace register_translation_unit { |
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18 | namespace stat_list_unit { |
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19 | |
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20 | |
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21 | #undef FUNCTION |
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22 | #define FUNCTION "Stat_List_unit::transition" |
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23 | void Stat_List_unit::transition (void) |
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24 | { |
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25 | log_printf(FUNC,Stat_List_unit,FUNCTION,"Begin"); |
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26 | |
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27 | if (PORT_READ(in_NRESET) == 0) |
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28 | { |
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29 | uint32_t gpr = 0; |
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30 | uint32_t spr = 0; |
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31 | |
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32 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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33 | { |
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34 | for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) |
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35 | gpr_stat_list [i][j].reset((gpr++)<_param->_nb_gpr_use_init); |
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36 | for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) |
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37 | spr_stat_list [i][j].reset((spr++)<_param->_nb_spr_use_init); |
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38 | } |
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39 | internal_GPR_PTR_FREE = 0; |
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40 | internal_SPR_PTR_FREE = 0; |
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41 | } |
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42 | else |
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43 | { |
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44 | // ===================================================== |
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45 | // =====[ INSERT ]====================================== |
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46 | // ===================================================== |
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47 | for (uint32_t i=0; i<_param->_nb_inst_insert; i++) |
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48 | if (PORT_READ(in_INSERT_VAL[i]) and internal_INSERT_ACK[i]) |
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49 | { |
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50 | if (PORT_READ(in_INSERT_READ_RA [i])) |
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51 | { |
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52 | Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RA_PHY [i]); |
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53 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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54 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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55 | gpr_stat_list [bank][reg].insert_read(); |
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56 | } |
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57 | |
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58 | if (PORT_READ(in_INSERT_READ_RB [i])) |
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59 | { |
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60 | Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RB_PHY [i]); |
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61 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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62 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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63 | gpr_stat_list [bank][reg].insert_read(); |
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64 | } |
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65 | |
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66 | if (PORT_READ(in_INSERT_READ_RC [i])) |
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67 | { |
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68 | Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RC_PHY [i]); |
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69 | uint32_t bank = num_reg >> _param->_shift_spr; |
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70 | uint32_t reg = num_reg & _param->_mask_spr ; |
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71 | spr_stat_list [bank][reg].insert_read(); |
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72 | } |
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73 | |
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74 | if (PORT_READ(in_INSERT_WRITE_RD [i])) |
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75 | { |
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76 | Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RD_PHY_NEW [i]); |
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77 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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78 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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79 | gpr_stat_list [bank][reg].insert_write(); |
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80 | } |
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81 | |
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82 | if (PORT_READ(in_INSERT_WRITE_RE [i])) |
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83 | { |
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84 | Tgeneral_address_t num_reg = PORT_READ(in_INSERT_NUM_REG_RE_PHY_NEW [i]); |
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85 | uint32_t bank = num_reg >> _param->_shift_spr; |
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86 | uint32_t reg = num_reg & _param->_mask_spr ; |
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87 | spr_stat_list [bank][reg].insert_write(); |
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88 | } |
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89 | } |
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90 | |
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91 | // ===================================================== |
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92 | // =====[ RETIRE ]====================================== |
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93 | // ===================================================== |
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94 | for (uint32_t i=0; i<_param->_nb_inst_retire; i++) |
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95 | if (PORT_READ(in_RETIRE_VAL[i]) and internal_RETIRE_ACK[i]) |
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96 | { |
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97 | if (PORT_READ(in_RETIRE_READ_RA [i])) |
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98 | { |
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99 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RA_PHY [i]); |
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100 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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101 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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102 | gpr_stat_list [bank][reg].retire_read(); |
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103 | } |
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104 | |
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105 | if (PORT_READ(in_RETIRE_READ_RB [i])) |
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106 | { |
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107 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RB_PHY [i]); |
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108 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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109 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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110 | gpr_stat_list [bank][reg].retire_read(); |
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111 | } |
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112 | |
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113 | if (PORT_READ(in_RETIRE_READ_RC [i])) |
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114 | { |
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115 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RC_PHY [i]); |
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116 | uint32_t bank = num_reg >> _param->_shift_spr; |
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117 | uint32_t reg = num_reg & _param->_mask_spr ; |
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118 | spr_stat_list [bank][reg].retire_read(); |
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119 | } |
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120 | |
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121 | if (PORT_READ(in_RETIRE_WRITE_RD [i])) |
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122 | { |
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123 | { |
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124 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_OLD [i]); |
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125 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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126 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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127 | gpr_stat_list [bank][reg].retire_write_old(); |
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128 | } |
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129 | { |
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130 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RD_PHY_NEW [i]); |
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131 | uint32_t bank = num_reg >> _param->_shift_gpr; |
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132 | uint32_t reg = num_reg & _param->_mask_gpr ; |
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133 | gpr_stat_list [bank][reg].retire_write_new(); |
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134 | } |
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135 | } |
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136 | |
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137 | if (PORT_READ(in_RETIRE_WRITE_RE [i])) |
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138 | { |
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139 | { |
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140 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_OLD [i]); |
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141 | uint32_t bank = num_reg >> _param->_shift_spr; |
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142 | uint32_t reg = num_reg & _param->_mask_spr ; |
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143 | spr_stat_list [bank][reg].retire_write_old(); |
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144 | } |
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145 | { |
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146 | Tgeneral_address_t num_reg = PORT_READ(in_RETIRE_NUM_REG_RE_PHY_NEW [i]); |
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147 | uint32_t bank = num_reg >> _param->_shift_spr; |
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148 | uint32_t reg = num_reg & _param->_mask_spr ; |
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149 | spr_stat_list [bank][reg].retire_write_new(); |
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150 | } |
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151 | } |
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152 | } |
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153 | |
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154 | for (uint32_t i=0; i<_param->_nb_reg_free; i++) |
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155 | { |
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156 | // ===================================================== |
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157 | // =====[ PUSH_GPR ]==================================== |
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158 | // ===================================================== |
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159 | if (internal_PUSH_GPR_VAL [i] and PORT_READ(in_PUSH_GPR_ACK [i])) |
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160 | gpr_stat_list[internal_PUSH_GPR_NUM_BANK [i]][internal_GPR_PTR_FREE].free(); |
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161 | |
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162 | // ===================================================== |
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163 | // =====[ PUSH_SPR ]==================================== |
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164 | // ===================================================== |
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165 | if (internal_PUSH_SPR_VAL [i] and PORT_READ(in_PUSH_SPR_ACK [i])) |
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166 | spr_stat_list[internal_PUSH_SPR_NUM_BANK [i]][internal_SPR_PTR_FREE].free(); |
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167 | } |
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168 | |
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169 | // Update pointer |
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170 | internal_GPR_PTR_FREE = ((internal_GPR_PTR_FREE==0)?_param->_nb_general_register_by_bank:internal_GPR_PTR_FREE)-1; |
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171 | internal_SPR_PTR_FREE = ((internal_SPR_PTR_FREE==0)?_param->_nb_special_register_by_bank:internal_SPR_PTR_FREE)-1; |
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172 | } |
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173 | |
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174 | // log_printf(TRACE,Stat_List_unit,FUNCTION,"Print gpr_stat_list :"); |
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175 | // for (uint32_t i=0; i<_param->_nb_bank; i++) |
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176 | // { |
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177 | // log_printf(TRACE,Stat_List_unit,FUNCTION," * Bank : %d",i); |
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178 | // for (uint32_t j=0; j<_param->_nb_general_register_by_bank; j++) |
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179 | // { |
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180 | // std::ostringstream str; |
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181 | // str << gpr_stat_list [i][j]; |
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182 | // log_printf(TRACE,Stat_List_unit,FUNCTION," [%d] %s",j,str.str().c_str()); |
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183 | |
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184 | // } |
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185 | // } |
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186 | // log_printf(TRACE,Stat_List_unit,FUNCTION,"Print spr_stat_list :"); |
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187 | // for (uint32_t i=0; i<_param->_nb_bank; i++) |
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188 | // { |
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189 | // log_printf(TRACE,Stat_List_unit,FUNCTION," * Bank : %d",i); |
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190 | // for (uint32_t j=0; j<_param->_nb_special_register_by_bank; j++) |
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191 | // { |
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192 | // std::ostringstream str; |
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193 | // str << spr_stat_list [i][j]; |
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194 | // log_printf(TRACE,Stat_List_unit,FUNCTION," [%d] %s",j,str.str().c_str()); |
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195 | // } |
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196 | // } |
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197 | |
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198 | #if defined(STATISTICS) or defined(VHDL_TESTBENCH) |
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199 | end_cycle (); |
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200 | #endif |
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201 | |
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202 | log_printf(FUNC,Stat_List_unit,FUNCTION,"End"); |
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203 | }; |
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204 | |
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205 | }; // end namespace stat_list_unit |
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206 | }; // end namespace register_translation_unit |
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207 | }; // end namespace rename_unit |
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208 | }; // end namespace ooo_engine |
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209 | }; // end namespace multi_ooo_engine |
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210 | }; // end namespace core |
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211 | |
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212 | }; // end namespace behavioural |
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213 | }; // end namespace morpheo |
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214 | #endif |
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