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test.cpp

Last change on this file was 128, checked in by rosiere, 16 years ago
1) Correct bug in link two signal 2) Fix error detected with valgrind 3) modif distexe script
Property svn:keywords set to `Id`
File size: 18.7 KB

Line
1	/*
2	* $Id: test.cpp 128 2009-06-26 08:43:23Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/include/test.h"
10	#include "Behavioural/include/Allocation.h"
11
12	void test (string name,
13	morpheo::behavioural::core::multi_ooo_engine::ooo_engine::special_register_unit::Parameters * _param)
14	{
15	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
16
17	#ifdef STATISTICS
18	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
19	#endif
20
21	Tusage_t _usage = USE_ALL;
22
23	// _usage = usage_unset(_usage,USE_SYSTEMC );
24	// _usage = usage_unset(_usage,USE_VHDL );
25	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
26	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
27	// _usage = usage_unset(_usage,USE_POSITION );
28	_usage = usage_unset(_usage,USE_STATISTICS );
29	// _usage = usage_unset(_usage,USE_INFORMATION );
30
31	Special_Register_unit * _Special_Register_unit = new Special_Register_unit
32	(name.c_str(),
33	#ifdef STATISTICS
34	_parameters_statistics,
35	#endif
36	_param,
37	_usage);
38
39	#ifdef SYSTEMC
40	if (usage_is_set(_usage,USE_SYSTEMC))
41	{
42	/*********************************************************************
43	* Déclarations des signaux
44	*********************************************************************/
45	string rename;
46
47	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
48	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
49
50	sc_signal<Tcontrol_t > ** in_SPR_ACCESS_VAL ;
51	sc_signal<Tcontrol_t > ** out_SPR_ACCESS_ACK ;
52	sc_signal<Tcontext_t > ** in_SPR_ACCESS_FRONT_END_ID;
53	sc_signal<Tcontext_t > ** in_SPR_ACCESS_CONTEXT_ID ;
54	sc_signal<Tcontrol_t > ** in_SPR_ACCESS_WEN ;
55	sc_signal<Tspr_address_t> ** in_SPR_ACCESS_NUM_GROUP ;
56	sc_signal<Tspr_address_t> ** in_SPR_ACCESS_NUM_REG ;
57	sc_signal<Tspr_t > ** in_SPR_ACCESS_WDATA ;
58	sc_signal<Tspr_t > ** out_SPR_ACCESS_RDATA ;
59	sc_signal<Tcontrol_t > ** out_SPR_ACCESS_INVALID ;
60
61	sc_signal<Tspr_t > *** out_SPR_READ_SR ;
62
63	sc_signal<Tcontrol_t > *** in_SPR_COMMIT_VAL ;
64	sc_signal<Tcontrol_t > *** out_SPR_COMMIT_ACK ;
65	sc_signal<Tcontrol_t > *** in_SPR_COMMIT_SR_F_VAL ;
66	sc_signal<Tcontrol_t > *** in_SPR_COMMIT_SR_F ;
67	sc_signal<Tcontrol_t > *** in_SPR_COMMIT_SR_CY_VAL ;
68	sc_signal<Tcontrol_t > *** in_SPR_COMMIT_SR_CY ;
69	sc_signal<Tcontrol_t > *** in_SPR_COMMIT_SR_OV_VAL ;
70	sc_signal<Tcontrol_t > *** in_SPR_COMMIT_SR_OV ;
71
72	sc_signal<Tcontrol_t > *** in_SPR_EVENT_VAL ;
73	sc_signal<Tcontrol_t > *** out_SPR_EVENT_ACK ;
74	sc_signal<Tspr_t > *** in_SPR_EVENT_EPCR ;
75	sc_signal<Tcontrol_t > *** in_SPR_EVENT_EEAR_WEN ;
76	sc_signal<Tspr_t > *** in_SPR_EVENT_EEAR ;
77	sc_signal<Tcontrol_t > *** in_SPR_EVENT_SR_DSX ;
78	sc_signal<Tcontrol_t > *** in_SPR_EVENT_SR_TO_ESR ;
79
80	ALLOC1_SC_SIGNAL( in_SPR_ACCESS_VAL ," in_SPR_ACCESS_VAL ",Tcontrol_t ,_param->_nb_inst_reexecute);
81	ALLOC1_SC_SIGNAL(out_SPR_ACCESS_ACK ,"out_SPR_ACCESS_ACK ",Tcontrol_t ,_param->_nb_inst_reexecute);
82	ALLOC1_SC_SIGNAL( in_SPR_ACCESS_FRONT_END_ID," in_SPR_ACCESS_FRONT_END_ID",Tcontext_t ,_param->_nb_inst_reexecute);
83	ALLOC1_SC_SIGNAL( in_SPR_ACCESS_CONTEXT_ID ," in_SPR_ACCESS_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_reexecute);
84	ALLOC1_SC_SIGNAL( in_SPR_ACCESS_WEN ," in_SPR_ACCESS_WEN ",Tcontrol_t ,_param->_nb_inst_reexecute);
85	ALLOC1_SC_SIGNAL( in_SPR_ACCESS_NUM_GROUP ," in_SPR_ACCESS_NUM_GROUP ",Tspr_address_t,_param->_nb_inst_reexecute);
86	ALLOC1_SC_SIGNAL( in_SPR_ACCESS_NUM_REG ," in_SPR_ACCESS_NUM_REG ",Tspr_address_t,_param->_nb_inst_reexecute);
87	ALLOC1_SC_SIGNAL( in_SPR_ACCESS_WDATA ," in_SPR_ACCESS_WDATA ",Tspr_t ,_param->_nb_inst_reexecute);
88	ALLOC1_SC_SIGNAL(out_SPR_ACCESS_RDATA ,"out_SPR_ACCESS_RDATA ",Tspr_t ,_param->_nb_inst_reexecute);
89	ALLOC1_SC_SIGNAL(out_SPR_ACCESS_INVALID ,"out_SPR_ACCESS_INVALID ",Tcontrol_t ,_param->_nb_inst_reexecute);
90	ALLOC2_SC_SIGNAL(out_SPR_READ_SR ,"out_SPR_READ_SR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]);
91	ALLOC2_SC_SIGNAL( in_SPR_COMMIT_VAL ," in_SPR_COMMIT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]);
92	ALLOC2_SC_SIGNAL(out_SPR_COMMIT_ACK ,"out_SPR_COMMIT_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]);
93	ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_F_VAL ," in_SPR_COMMIT_SR_F_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]);
94	ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_F ," in_SPR_COMMIT_SR_F ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]);
95	ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_CY_VAL ," in_SPR_COMMIT_SR_CY_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]);
96	ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_CY ," in_SPR_COMMIT_SR_CY ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]);
97	ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_OV_VAL ," in_SPR_COMMIT_SR_OV_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]);
98	ALLOC2_SC_SIGNAL( in_SPR_COMMIT_SR_OV ," in_SPR_COMMIT_SR_OV ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]);
99
100	ALLOC2_SC_SIGNAL( in_SPR_EVENT_VAL ," in_SPR_EVENT_VAL ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]);
101	ALLOC2_SC_SIGNAL(out_SPR_EVENT_ACK ,"out_SPR_EVENT_ACK ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]);
102	ALLOC2_SC_SIGNAL( in_SPR_EVENT_EPCR ," in_SPR_EVENT_EPCR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]);
103	ALLOC2_SC_SIGNAL( in_SPR_EVENT_EEAR_WEN ," in_SPR_EVENT_EEAR_WEN ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]);
104	ALLOC2_SC_SIGNAL( in_SPR_EVENT_EEAR ," in_SPR_EVENT_EEAR ",Tspr_t ,_param->_nb_front_end,_param->_nb_context[it1]);
105	ALLOC2_SC_SIGNAL( in_SPR_EVENT_SR_DSX ," in_SPR_EVENT_SR_DSX ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]);
106	ALLOC2_SC_SIGNAL( in_SPR_EVENT_SR_TO_ESR ," in_SPR_EVENT_SR_TO_ESR ",Tcontrol_t ,_param->_nb_front_end,_param->_nb_context[it1]);
107
108	/********************************************************
109	* Instanciation
110	********************************************************/
111
112	msg(_("<%s> : Instanciation of _Special_Register_unit.\n"),name.c_str());
113
114	((_Special_Register_unit->in_CLOCK)) ((in_CLOCK));
115	((_Special_Register_unit->in_NRESET)) ((in_NRESET));
116
117	INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_VAL ,_param->_nb_inst_reexecute);
118	INSTANCE1_SC_SIGNAL(_Special_Register_unit,out_SPR_ACCESS_ACK ,_param->_nb_inst_reexecute);
119	INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_WEN ,_param->_nb_inst_reexecute);
120	if (_param->_have_port_front_end_id)
121	INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_FRONT_END_ID ,_param->_nb_inst_reexecute);
122	if (_param->_have_port_context_id)
123	INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_CONTEXT_ID ,_param->_nb_inst_reexecute);
124	INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_NUM_GROUP ,_param->_nb_inst_reexecute);
125	INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_NUM_REG ,_param->_nb_inst_reexecute);
126	INSTANCE1_SC_SIGNAL(_Special_Register_unit, in_SPR_ACCESS_WDATA ,_param->_nb_inst_reexecute);
127	INSTANCE1_SC_SIGNAL(_Special_Register_unit,out_SPR_ACCESS_RDATA ,_param->_nb_inst_reexecute);
128	INSTANCE1_SC_SIGNAL(_Special_Register_unit,out_SPR_ACCESS_INVALID ,_param->_nb_inst_reexecute);
129
130	INSTANCE2_SC_SIGNAL(_Special_Register_unit,out_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1]);
131
132	INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]);
133	INSTANCE2_SC_SIGNAL(_Special_Register_unit,out_SPR_COMMIT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]);
134	INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_F_VAL ,_param->_nb_front_end, _param->_nb_context[it1]);
135	INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_F ,_param->_nb_front_end, _param->_nb_context[it1]);
136	INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_CY_VAL ,_param->_nb_front_end, _param->_nb_context[it1]);
137	INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_CY ,_param->_nb_front_end, _param->_nb_context[it1]);
138	INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_OV_VAL ,_param->_nb_front_end, _param->_nb_context[it1]);
139	INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_COMMIT_SR_OV ,_param->_nb_front_end, _param->_nb_context[it1]);
140
141	INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]);
142	INSTANCE2_SC_SIGNAL(_Special_Register_unit,out_SPR_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]);
143	INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_EPCR ,_param->_nb_front_end, _param->_nb_context[it1]);
144	INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_EEAR_WEN ,_param->_nb_front_end, _param->_nb_context[it1]);
145	INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_EEAR ,_param->_nb_front_end, _param->_nb_context[it1]);
146	INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_SR_DSX ,_param->_nb_front_end, _param->_nb_context[it1]);
147	INSTANCE2_SC_SIGNAL(_Special_Register_unit, in_SPR_EVENT_SR_TO_ESR ,_param->_nb_front_end, _param->_nb_context[it1]);
148
149	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
150
151	Time * _time = new Time();
152
153	/********************************************************
154	* Simulation - Begin
155	********************************************************/
156
157	// Initialisation
158
159	const uint32_t seed = 0;
160	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
161
162	srand(seed);
163
164	const int32_t percent_transaction_spr_access = 75;
165	const int32_t percent_transaction_spr_commit = 75;
166	const int32_t percent_transaction_spr_event = 75;
167
168	SC_START(0);
169	LABEL("Initialisation");
170
171	LABEL("Reset");
172	in_NRESET->write(0);
173	SC_START(5);
174	in_NRESET->write(1);
175
176	Tspr_t sr [_param->_nb_front_end][_param->_max_nb_context];
177	Tspr_t dccr [_param->_nb_front_end][_param->_max_nb_context];
178
179	for (uint32_t i=0; i<_param->_nb_front_end; i++)
180	for (uint32_t j=0; j<_param->_nb_context[i]; j++)
181	{
182	sr [i][j] = 0x00008001;
183	dccr [i][j] = 0x0;
184	TEST(Tspr_t, out_SPR_READ_SR [i][j]->read(), sr [i][j]);
185	}
186
187	LABEL("Loop of Test");
188
189	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
190	{
191	LABEL("Iteration %d",iteration);
192
193	Tcontext_t front_end = rand()%_param->_nb_front_end;
194	Tcontext_t context = rand()%_param->_nb_context[front_end];
195	uint32_t port = rand()%_param->_nb_inst_reexecute;
196	uint32_t config = rand()%3;
197	Tcontrol_t wen = rand()%2;
198	Tspr_t wdata = rand();
199	{
200	in_SPR_ACCESS_VAL [port]->write((rand()%100)<percent_transaction_spr_access);
201	in_SPR_ACCESS_FRONT_END_ID [port]->write(front_end);
202	in_SPR_ACCESS_CONTEXT_ID [port]->write(context);
203
204	switch (config)
205	{
206	case 0 :
207	wen = 0;
208	in_SPR_ACCESS_NUM_GROUP [port]->write(0);
209	in_SPR_ACCESS_NUM_REG [port]->write(17);
210	break;
211	case 1 :
212	in_SPR_ACCESS_NUM_GROUP [port]->write(3);
213	in_SPR_ACCESS_NUM_REG [port]->write(0);
214	break;
215	case 2 :
216	in_SPR_ACCESS_NUM_GROUP [port]->write(5);
217	in_SPR_ACCESS_NUM_REG [port]->write(1);
218	break;
219	}
220
221	in_SPR_ACCESS_WEN [port]->write(wen);
222	in_SPR_ACCESS_WDATA [port]->write(wdata);
223	}
224
225	{
226	in_SPR_COMMIT_VAL [front_end][context]->write((rand()%100)<percent_transaction_spr_commit);
227	in_SPR_COMMIT_SR_F_VAL [front_end][context]->write((rand()%100)<percent_transaction_spr_commit);
228	in_SPR_COMMIT_SR_CY_VAL [front_end][context]->write((rand()%100)<percent_transaction_spr_commit);
229	in_SPR_COMMIT_SR_OV_VAL [front_end][context]->write((rand()%100)<percent_transaction_spr_commit);
230	in_SPR_COMMIT_SR_F [front_end][context]->write(rand()%2);
231	in_SPR_COMMIT_SR_CY [front_end][context]->write(rand()%2);
232	in_SPR_COMMIT_SR_OV [front_end][context]->write(rand()%2);
233	}
234
235	{
236	in_SPR_EVENT_VAL [front_end][context]->write((rand()%100)<percent_transaction_spr_event);
237	in_SPR_EVENT_EPCR [front_end][context]->write(rand());
238	in_SPR_EVENT_EEAR_WEN [front_end][context]->write(rand()%2);
239	in_SPR_EVENT_EEAR [front_end][context]->write(rand());
240	in_SPR_EVENT_SR_DSX [front_end][context]->write(rand()%2);
241	in_SPR_EVENT_SR_TO_ESR [front_end][context]->write(rand()%2);
242	}
243
244	SC_START(0);
245
246	if (in_SPR_ACCESS_VAL [port]->read() and out_SPR_ACCESS_ACK [port]->read())
247	{
248	LABEL("SPR_ACCESS [%d] - Transaction accepted.",port);
249	LABEL(" * front_end : %d" ,(unsigned int)front_end);
250	LABEL(" * context : %d" ,(unsigned int)context );
251	LABEL(" * config : %d" ,(unsigned int)config );
252	LABEL(" * wen : %d" ,(unsigned int)wen );
253	LABEL(" * wdata : %d" ,(unsigned int)wdata&0xff );
254
255	switch (config)
256	{
257	case 0 :
258	TEST(Tspr_t ,out_SPR_ACCESS_RDATA [port]->read(),sr[front_end][context]);
259	TEST(Tcontrol_t,out_SPR_ACCESS_INVALID [port]->read(),0);
260	break;
261	case 1 :
262	if (sr[front_end][context] & 1)
263	{
264	TEST(Tspr_t ,out_SPR_ACCESS_RDATA [port]->read(),dccr[front_end][context]&0xff);
265	TEST(Tcontrol_t,out_SPR_ACCESS_INVALID [port]->read(),0);
266
267	if (wen)
268	dccr[front_end][context] = wdata;
269	}
270	else
271	TEST(Tcontrol_t,out_SPR_ACCESS_INVALID [port]->read(),1);
272	break;
273	case 2 :
274	TEST(Tcontrol_t,out_SPR_ACCESS_INVALID [port]->read(),1);
275	break;
276	}
277	}
278
279	if (in_SPR_COMMIT_VAL [front_end][context]->read() and out_SPR_COMMIT_ACK [front_end][context]->read())
280	{
281	LABEL("SPR_COMMIT [%d][%d] - Transaction accepted.",front_end,context);
282	LABEL(" * cy_val : %d",in_SPR_COMMIT_SR_CY_VAL [front_end][context]->read());
283	LABEL(" * cy : %d",in_SPR_COMMIT_SR_CY [front_end][context]->read());
284	LABEL(" * ov_val : %d",in_SPR_COMMIT_SR_OV_VAL [front_end][context]->read());
285	LABEL(" * ov : %d",in_SPR_COMMIT_SR_OV [front_end][context]->read());
286	LABEL(" * f_val : %d",in_SPR_COMMIT_SR_F_VAL [front_end][context]->read());
287	LABEL(" * f : %d",in_SPR_COMMIT_SR_F [front_end][context]->read());
288	LABEL(" * sr (old) : 0x%d",sr[front_end][context]);
289	if (in_SPR_COMMIT_SR_CY_VAL [front_end][context]->read())
290	CHANGE_FLAG(sr[front_end][context], 10, in_SPR_COMMIT_SR_CY [front_end][context]->read());
291
292	if (in_SPR_COMMIT_SR_OV_VAL [front_end][context]->read())
293	CHANGE_FLAG(sr[front_end][context], 11, in_SPR_COMMIT_SR_OV [front_end][context]->read());
294
295	if (in_SPR_COMMIT_SR_F_VAL [front_end][context]->read())
296	CHANGE_FLAG(sr[front_end][context], 9, in_SPR_COMMIT_SR_F [front_end][context]->read());
297	LABEL(" * sr (new) : 0x%d",sr[front_end][context]);
298	}
299
300	if (in_SPR_EVENT_VAL [front_end][context]->read() and out_SPR_EVENT_ACK [front_end][context]->read())
301	{
302	LABEL("SPR_EVENT [%d][%d] - Transaction accepted.",front_end,context);
303
304	CHANGE_FLAG(sr[front_end][context], 13, in_SPR_EVENT_SR_DSX [front_end][context]->read());
305	}
306
307	SC_START(1);
308
309	for (uint32_t i=0; i<_param->_nb_front_end; i++)
310	for (uint32_t j=0; j<_param->_nb_context[i]; j++)
311	TEST(Tspr_t, out_SPR_READ_SR [i][j]->read(), sr [i][j]);
312
313	in_SPR_ACCESS_VAL [port]->write(0);
314	in_SPR_COMMIT_VAL [front_end][context]->write(0);
315	}
316
317	/********************************************************
318	* Simulation - End
319	********************************************************/
320
321	TEST_OK ("End of Simulation");
322	delete _time;
323
324	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
325
326	delete in_CLOCK;
327	delete in_NRESET;
328
329	DELETE1_SC_SIGNAL( in_SPR_ACCESS_VAL ,_param->_nb_inst_reexecute);
330	DELETE1_SC_SIGNAL(out_SPR_ACCESS_ACK ,_param->_nb_inst_reexecute);
331	DELETE1_SC_SIGNAL( in_SPR_ACCESS_WEN ,_param->_nb_inst_reexecute);
332	DELETE1_SC_SIGNAL( in_SPR_ACCESS_CONTEXT_ID ,_param->_nb_inst_reexecute);
333	DELETE1_SC_SIGNAL( in_SPR_ACCESS_FRONT_END_ID ,_param->_nb_inst_reexecute);
334	DELETE1_SC_SIGNAL( in_SPR_ACCESS_NUM_GROUP ,_param->_nb_inst_reexecute);
335	DELETE1_SC_SIGNAL( in_SPR_ACCESS_NUM_REG ,_param->_nb_inst_reexecute);
336	DELETE1_SC_SIGNAL( in_SPR_ACCESS_WDATA ,_param->_nb_inst_reexecute);
337	DELETE1_SC_SIGNAL(out_SPR_ACCESS_RDATA ,_param->_nb_inst_reexecute);
338	DELETE1_SC_SIGNAL(out_SPR_ACCESS_INVALID ,_param->_nb_inst_reexecute);
339
340	DELETE2_SC_SIGNAL(out_SPR_READ_SR ,_param->_nb_front_end, _param->_nb_context[it1]);
341
342	DELETE2_SC_SIGNAL( in_SPR_COMMIT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]);
343	DELETE2_SC_SIGNAL(out_SPR_COMMIT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]);
344	DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_F_VAL ,_param->_nb_front_end, _param->_nb_context[it1]);
345	DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_F ,_param->_nb_front_end, _param->_nb_context[it1]);
346	DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_CY_VAL ,_param->_nb_front_end, _param->_nb_context[it1]);
347	DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_CY ,_param->_nb_front_end, _param->_nb_context[it1]);
348	DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_OV_VAL ,_param->_nb_front_end, _param->_nb_context[it1]);
349	DELETE2_SC_SIGNAL( in_SPR_COMMIT_SR_OV ,_param->_nb_front_end, _param->_nb_context[it1]);
350
351	DELETE2_SC_SIGNAL( in_SPR_EVENT_VAL ,_param->_nb_front_end, _param->_nb_context[it1]);
352	DELETE2_SC_SIGNAL(out_SPR_EVENT_ACK ,_param->_nb_front_end, _param->_nb_context[it1]);
353	DELETE2_SC_SIGNAL( in_SPR_EVENT_EPCR ,_param->_nb_front_end, _param->_nb_context[it1]);
354	DELETE2_SC_SIGNAL( in_SPR_EVENT_EEAR_WEN ,_param->_nb_front_end, _param->_nb_context[it1]);
355	DELETE2_SC_SIGNAL( in_SPR_EVENT_EEAR ,_param->_nb_front_end, _param->_nb_context[it1]);
356	DELETE2_SC_SIGNAL( in_SPR_EVENT_SR_DSX ,_param->_nb_front_end, _param->_nb_context[it1]);
357	DELETE2_SC_SIGNAL( in_SPR_EVENT_SR_TO_ESR ,_param->_nb_front_end, _param->_nb_context[it1]);
358	}
359	#endif
360
361	delete _Special_Register_unit;
362	#ifdef STATISTICS
363	delete _parameters_statistics;
364	#endif
365	}

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/SelfTest/src/test.cpp

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