[88] | 1 | /* |
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| 2 | * $Id: Special_Register_unit_allocation.cpp 88 2008-12-10 18:31:39Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | #include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h" |
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| 9 | #include "Behavioural/include/Allocation.h" |
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| 10 | #include "Common/include/Max.h" |
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| 11 | |
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| 12 | namespace morpheo { |
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| 13 | namespace behavioural { |
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| 14 | namespace core { |
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| 15 | namespace multi_ooo_engine { |
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| 16 | namespace ooo_engine { |
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| 17 | namespace special_register_unit { |
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| 18 | |
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| 19 | |
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| 20 | |
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| 21 | #undef FUNCTION |
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| 22 | #define FUNCTION "Special_Register_unit::allocation" |
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| 23 | void Special_Register_unit::allocation ( |
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| 24 | #ifdef STATISTICS |
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| 25 | morpheo::behavioural::Parameters_Statistics * param_statistics |
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| 26 | #else |
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| 27 | void |
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| 28 | #endif |
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| 29 | ) |
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| 30 | { |
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| 31 | log_begin(Special_Register_unit,FUNCTION); |
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| 32 | |
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| 33 | _component = new Component (_usage); |
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| 34 | |
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| 35 | Entity * entity = _component->set_entity (_name |
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| 36 | ,"Special_Register_unit" |
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| 37 | #ifdef POSITION |
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| 38 | ,COMBINATORY |
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| 39 | #endif |
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| 40 | ); |
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| 41 | |
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| 42 | _interfaces = entity->set_interfaces(); |
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| 43 | |
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| 44 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 45 | { |
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| 46 | Interface * interface = _interfaces->set_interface("" |
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| 47 | #ifdef POSITION |
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| 48 | ,IN |
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| 49 | ,SOUTH, |
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| 50 | _("Generalist interface") |
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| 51 | #endif |
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| 52 | ); |
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| 53 | |
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| 54 | in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); |
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| 55 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); |
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| 56 | } |
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| 57 | |
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| 58 | // ~~~~~[ Interface : "spr_access" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 59 | { |
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| 60 | ALLOC1_INTERFACE("spr_access",IN,WEST, _("Access from reexecute_unit"), _param->_nb_inst_reexecute); |
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| 61 | |
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| 62 | ALLOC1_VALACK_IN ( in_SPR_ACCESS_VAL ,VAL); |
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| 63 | ALLOC1_VALACK_OUT(out_SPR_ACCESS_ACK ,ACK); |
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| 64 | ALLOC1_SIGNAL_IN ( in_SPR_ACCESS_WEN ,"wen" ,Tcontrol_t ,1); |
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| 65 | ALLOC1_SIGNAL_IN ( in_SPR_ACCESS_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); |
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| 66 | ALLOC1_SIGNAL_IN ( in_SPR_ACCESS_FRONT_END_ID ,"front_end_id",Tcontext_t ,_param->_size_front_end_id); |
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| 67 | ALLOC1_SIGNAL_IN ( in_SPR_ACCESS_NUM_GROUP ,"num_group" ,Tspr_address_t ,_param->_size_special_address_group ); |
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| 68 | ALLOC1_SIGNAL_IN ( in_SPR_ACCESS_NUM_REG ,"num_reg" ,Tspr_address_t ,_param->_size_special_address_register); |
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| 69 | ALLOC1_SIGNAL_IN ( in_SPR_ACCESS_WDATA ,"wdata" ,Tspr_t ,_param->_size_spr); |
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| 70 | ALLOC1_SIGNAL_OUT(out_SPR_ACCESS_RDATA ,"rdata" ,Tspr_t ,_param->_size_spr); |
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| 71 | ALLOC1_SIGNAL_OUT(out_SPR_ACCESS_INVALID ,"invalid" ,Tcontrol_t ,1); |
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| 72 | } |
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| 73 | |
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| 74 | // ~~~~~[ Interface : "spr_read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 75 | { |
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| 76 | ALLOC2_INTERFACE("spr_read",OUT,WEST, _("Output for a spr bit field."), _param->_nb_front_end, _param->_nb_context[it1]); |
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| 77 | |
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| 78 | _ALLOC2_SIGNAL_OUT(out_SPR_READ_SR ,"sr",Tspr_t,_param->_size_spr, _param->_nb_front_end, _param->_nb_context[it1]); |
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| 79 | } |
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| 80 | |
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| 81 | // ~~~~~[ Interface : "spr_commit" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 82 | { |
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| 83 | ALLOC2_INTERFACE("spr_commit",IN,WEST, _("Commit instruction to change SR's flags."), _param->_nb_front_end, _param->_nb_context[it1]); |
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| 84 | |
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| 85 | _ALLOC2_VALACK_IN ( in_SPR_COMMIT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 86 | _ALLOC2_VALACK_OUT(out_SPR_COMMIT_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 87 | _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_F_VAL ,"sr_f_val" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 88 | _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_F ,"sr_f" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 89 | _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_CY_VAL ,"sr_cy_val" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 90 | _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_CY ,"sr_cy" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 91 | _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_OV_VAL ,"sr_ov_val" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 92 | _ALLOC2_SIGNAL_IN ( in_SPR_COMMIT_SR_OV ,"sr_ov" ,Tcontrol_t ,1,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 93 | } |
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| 94 | |
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| 95 | // ~~~~~[ Interface "spr_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 96 | { |
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| 97 | ALLOC2_INTERFACE("spr_event",IN,WEST, _("Event change a lot of exception."), _param->_nb_front_end, _param->_nb_context[it1]); |
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| 98 | |
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| 99 | _ALLOC2_VALACK_IN ( in_SPR_EVENT_VAL ,VAL,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 100 | _ALLOC2_VALACK_OUT(out_SPR_EVENT_ACK ,ACK,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 101 | _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_EPCR ,"EPCR" ,Tspr_t ,_param->_size_spr,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 102 | _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_EEAR_WEN ,"EEAR_WEN" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 103 | _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_EEAR ,"EEAR" ,Tspr_t ,_param->_size_spr,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 104 | _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_SR_DSX ,"SR_DSX" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 105 | _ALLOC2_SIGNAL_IN ( in_SPR_EVENT_SR_TO_ESR ,"SR_TO_ESR" ,Tcontrol_t ,1 ,_param->_nb_front_end, _param->_nb_context[it1]); |
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| 106 | } |
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| 107 | |
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| 108 | if (usage_is_set(_usage,USE_SYSTEMC)) |
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| 109 | { |
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| 110 | // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 111 | internal_SPR_ACCESS_ACK = new Tcontrol_t [_param->_nb_inst_reexecute]; |
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| 112 | internal_SPR_COMMIT_ACK = new Tcontrol_t * [_param->_nb_front_end]; |
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| 113 | internal_SPR_EVENT_ACK = new Tcontrol_t * [_param->_nb_front_end]; |
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| 114 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 115 | { |
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| 116 | internal_SPR_COMMIT_ACK [i] = new Tcontrol_t [_param->_nb_context [i]]; |
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| 117 | internal_SPR_EVENT_ACK [i] = new Tcontrol_t [_param->_nb_context [i]]; |
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| 118 | } |
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| 119 | } |
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| 120 | |
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| 121 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 122 | _spr_access_mode = new SPR_access_mode ** [_param->_nb_front_end]; |
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| 123 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 124 | { |
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| 125 | _spr_access_mode [i] = new SPR_access_mode * [_param->_nb_context[i]]; |
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| 126 | |
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| 127 | for (uint32_t j=0; j<_param->_nb_context[i]; j++) |
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| 128 | { |
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| 129 | _spr_access_mode [i][j] = new SPR_access_mode; |
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| 130 | |
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| 131 | for (uint32_t k=0; k<NB_GROUP; k++) |
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| 132 | if (_param->_implement_group [i][j][k]) |
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| 133 | _spr_access_mode [i][j]->implement_group(k); |
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| 134 | } |
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| 135 | } |
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| 136 | |
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| 137 | _spr = new SPR **** [_param->_nb_front_end]; |
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| 138 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 139 | { |
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| 140 | _spr [i] = new SPR *** [_param->_nb_context[i]]; |
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| 141 | |
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| 142 | for (uint32_t j=0; j<_param->_nb_context[i]; j++) |
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| 143 | { |
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| 144 | _spr [i][j] = new SPR ** [NB_GROUP]; |
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| 145 | |
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| 146 | for (uint32_t k=0; k<NB_GROUP; k++) |
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| 147 | if (_param->_implement_group [i][j][k]) |
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| 148 | { |
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| 149 | _spr [i][j][k] = new SPR * [NB_REG_GROUP[k]]; |
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| 150 | |
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| 151 | switch (k) |
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| 152 | { |
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| 153 | case GROUP_SYSTEM_AND_CONTROL : |
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| 154 | { |
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| 155 | _spr [i][j][k][SPR_VR ] = new VR (i,j,_param); |
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| 156 | _spr [i][j][k][SPR_UPR ] = new UPR (i,j,_param); |
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| 157 | _spr [i][j][k][SPR_CPUCFGR ] = new CPUCFGR (i,j,_param); |
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| 158 | _spr [i][j][k][SPR_DMMUCFGR ] = new DMMUCFGR (i,j,_param); |
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| 159 | _spr [i][j][k][SPR_IMMUCFGR ] = new IMMUCFGR (i,j,_param); |
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| 160 | _spr [i][j][k][SPR_DCCFGR ] = new DCCFGR (i,j,_param); |
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| 161 | _spr [i][j][k][SPR_ICCFGR ] = new ICCFGR (i,j,_param); |
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| 162 | _spr [i][j][k][SPR_DCFGR ] = new DCFGR (i,j,_param); |
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| 163 | _spr [i][j][k][SPR_PCCFGR ] = new PCCFGR (i,j,_param); |
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| 164 | _spr [i][j][k][SPR_NPC ] = new NPC (i,j,_param); |
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| 165 | _spr [i][j][k][SPR_SR ] = new SR (i,j,_param); |
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| 166 | _spr [i][j][k][SPR_PPC ] = new PPC (i,j,_param); |
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| 167 | _spr [i][j][k][SPR_CID ] = new CID (i,j,_param); |
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| 168 | _spr [i][j][k][SPR_FPCSR ] = new FPCSR (i,j,_param); |
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| 169 | _spr [i][j][k][SPR_EPCR ] = new EPCR (i,j,_param); |
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| 170 | _spr [i][j][k][SPR_EEAR ] = new EEAR (i,j,_param); |
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| 171 | _spr [i][j][k][SPR_ESR ] = new ESR (i,j,_param); |
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| 172 | // _spr [i][j][k][SPR_GPR ] = new GPR (i,j,_param); |
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| 173 | |
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| 174 | break; |
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| 175 | } |
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| 176 | case GROUP_DCACHE : |
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| 177 | { |
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| 178 | _spr [i][j][k][SPR_DCCR ] = new DCCR (i,j,_param); |
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| 179 | _spr [i][j][k][SPR_DCBPR ] = new DCBPR (i,j,_param); |
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| 180 | _spr [i][j][k][SPR_DCBFR ] = new DCBFR (i,j,_param); |
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| 181 | _spr [i][j][k][SPR_DCBIR ] = new DCBIR (i,j,_param); |
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| 182 | _spr [i][j][k][SPR_DCBWR ] = new DCBWR (i,j,_param); |
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| 183 | _spr [i][j][k][SPR_DCBLR ] = new DCBLR (i,j,_param); |
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| 184 | |
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| 185 | break; |
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| 186 | } |
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| 187 | case GROUP_DMMU : |
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| 188 | case GROUP_IMMU : |
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| 189 | case GROUP_ICACHE : |
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| 190 | case GROUP_DEBUG : |
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| 191 | case GROUP_PERFORMANCE_COUNTER : |
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| 192 | case GROUP_POWER_MANAGEMENT : |
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| 193 | case GROUP_PIC : |
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| 194 | case GROUP_TICK_TIMER : |
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| 195 | case GROUP_FLOATING_POINT : |
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| 196 | |
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| 197 | case GROUP_MAC : |
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| 198 | case GROUP_RESERVED_1 : |
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| 199 | case GROUP_RESERVED_2 : |
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| 200 | case GROUP_RESERVED_3 : |
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| 201 | case GROUP_RESERVED_4 : |
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| 202 | case GROUP_RESERVED_5 : |
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| 203 | case GROUP_RESERVED_6 : |
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| 204 | case GROUP_RESERVED_7 : |
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| 205 | case GROUP_RESERVED_8 : |
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| 206 | case GROUP_RESERVED_9 : |
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| 207 | case GROUP_RESERVED_10 : |
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| 208 | case GROUP_RESERVED_11 : |
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| 209 | case GROUP_RESERVED_12 : |
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| 210 | case GROUP_CUSTOM_1 : |
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| 211 | case GROUP_CUSTOM_2 : |
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| 212 | case GROUP_CUSTOM_3 : |
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| 213 | case GROUP_CUSTOM_4 : |
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| 214 | case GROUP_CUSTOM_5 : |
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| 215 | case GROUP_CUSTOM_6 : |
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| 216 | case GROUP_CUSTOM_7 : |
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| 217 | case GROUP_CUSTOM_8 : |
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| 218 | default : |
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| 219 | { |
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| 220 | for (uint32_t l=0; l<NB_REG_GROUP[k]; l++) |
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| 221 | _spr [i][j][k][l] = NULL; |
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| 222 | } |
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| 223 | } |
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| 224 | } |
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| 225 | else |
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| 226 | _spr [i][j][k] = NULL; |
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| 227 | } |
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| 228 | } |
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| 229 | |
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| 230 | for (uint32_t i=0; i<_param->_nb_front_end; i++) |
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| 231 | for (uint32_t j=0; j<_param->_nb_context[i]; j++) |
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| 232 | for (uint32_t k=0; k<NB_GROUP; k++) |
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| 233 | if (_param->_implement_group [i][j][k]) |
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| 234 | for (uint32_t l=0; l<NB_REG_GROUP[k]; l++) |
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| 235 | if (_spr [i][j][k][l] == NULL) |
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| 236 | _spr_access_mode [i][j]->invalid_register (k,l); |
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| 237 | |
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| 238 | #ifdef POSITION |
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| 239 | if (usage_is_set(_usage,USE_POSITION)) |
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| 240 | _component->generate_file(); |
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| 241 | #endif |
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| 242 | |
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| 243 | log_end(Special_Register_unit,FUNCTION); |
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| 244 | }; |
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| 245 | |
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| 246 | }; // end namespace special_register_unit |
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| 247 | }; // end namespace ooo_engine |
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| 248 | }; // end namespace multi_ooo_engine |
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| 249 | }; // end namespace core |
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| 250 | |
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| 251 | }; // end namespace behavioural |
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| 252 | }; // end namespace morpheo |
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