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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/src/Special_Register_unit_transition.cpp @ 98

Last change on this file since 98 was 98, checked in by rosiere, 16 years ago
1) Fix bug (read unit, RAT -> write in R0, SPR desallocation ...) 2) Change VHDL Execute_queue -> use Generic/Queue? 3) Complete document on VHDL generation 4) Add soc test
Property svn:keywords set to `Id`
File size: 5.7 KB

Line
1	#ifdef SYSTEMC
2	/*
3	* $Id: Special_Register_unit_transition.cpp 98 2008-12-31 10:18:08Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_OOO_Engine/OOO_Engine/Special_Register_unit/include/Special_Register_unit.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_ooo_engine {
15	namespace ooo_engine {
16	namespace special_register_unit {
17
18
19	#undef FUNCTION
20	#define FUNCTION "Special_Register_unit::transition"
21	void Special_Register_unit::transition (void)
22	{
23	log_begin(Special_Register_unit,FUNCTION);
24	log_function(Special_Register_unit,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	for (uint32_t i=0; i<_param->_nb_front_end; i++)
29	for (uint32_t j=0; j<_param->_nb_context[i]; j++)
30	for (uint32_t k=0; k<NB_GROUP; k++)
31	if (_param->_implement_group [i][j][k])
32	for (uint32_t l=0; l<NB_REG_GROUP[k]; l++)
33	if (_spr_access_mode [i][j]->exist(k,l))
34	{
35	#ifdef DEBUG_TEST
36	if (_spr [i][j][k] == NULL)
37	throw ERRORMORPHEO(FUNCTION,toString(_("Group [%d] is not implemented.\n"),k));
38	if (_spr [i][j][k][l] == NULL)
39	throw ERRORMORPHEO(FUNCTION,toString(_("Register [%d][%d] is not implemented.\n"),k,l));
40	#endif
41	log_printf(TRACE,Special_Register_unit,FUNCTION," * Reset SPR [%d][%d][%d][%d]",i,j,k,l);
42	_spr [i][j][k][l]->reset();
43	}
44
45	}
46	else
47	{
48	// ===================================================================
49	// =====[ SPR_ACCESS ]================================================
50	// ===================================================================
51	for (uint32_t i=0; i<_param->_nb_inst_reexecute; i++)
52	if (PORT_READ(in_SPR_ACCESS_VAL [i]) and internal_SPR_ACCESS_ACK [i])
53	if (PORT_READ(in_SPR_ACCESS_WEN [i]))
54	{
55	log_printf(TRACE,Special_Register_unit,FUNCTION," * SPR_ACCESS [%d]",i);
56
57	Tcontext_t front_end_id = (_param->_have_port_front_end_id)?PORT_READ(in_SPR_ACCESS_FRONT_END_ID [i]):0;
58	Tcontext_t context_id = (_param->_have_port_context_id )?PORT_READ(in_SPR_ACCESS_CONTEXT_ID [i]):0;
59	Tspr_address_t num_group = PORT_READ(in_SPR_ACCESS_NUM_GROUP [i]);
60	Tspr_address_t num_reg = PORT_READ(in_SPR_ACCESS_NUM_REG [i]);
61
62	log_printf(TRACE,Special_Register_unit,FUNCTION," * front_end_id : %d",front_end_id);
63	log_printf(TRACE,Special_Register_unit,FUNCTION," * context_id : %d",context_id );
64	log_printf(TRACE,Special_Register_unit,FUNCTION," * num_group : %d",num_group );
65	log_printf(TRACE,Special_Register_unit,FUNCTION," * num_reg : %d",num_reg );
66
67	SR * sr = static_cast<SR*>(_spr [front_end_id][context_id][GROUP_SYSTEM_AND_CONTROL][SPR_SR]);
68
69	Tcontrol_t sm = sr->sm ;
70	Tcontrol_t sumra = sr->sumra;
71	Tcontrol_t valid = _spr_access_mode [front_end_id][context_id]->write(spr_address_t(num_group,num_reg),
72	sm,
73	sumra);
74	log_printf(TRACE,Special_Register_unit,FUNCTION," * SM : %d",sm);
75	log_printf(TRACE,Special_Register_unit,FUNCTION," * SUMRA : %d",sumra);
76	log_printf(TRACE,Special_Register_unit,FUNCTION," * valid : %d",valid);
77
78	if (valid)
79	{
80	Tspr_t wdata = PORT_READ(in_SPR_ACCESS_WDATA [i]);
81
82	log_printf(TRACE,Special_Register_unit,FUNCTION," * wdata : %.8x",wdata);
83
84	_spr[front_end_id][context_id][num_group][num_reg]->write(wdata);
85	}
86
87	}
88
89	// ===================================================================
90	// =====[ SPR_COMMIT ]-===============================================
91	// ===================================================================
92	for (uint32_t i=0; i<_param->_nb_front_end; i++)
93	for (uint32_t j=0; j<_param->_nb_context[i]; j++)
94	{
95	if (PORT_READ(in_SPR_COMMIT_VAL [i][j])) // out_SPR_COMMIT_ACK [i][j]
96	{
97	SR * sr = static_cast<SR*>(_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]);
98
99	if (PORT_READ(in_SPR_COMMIT_SR_F_VAL [i][j]))
100	sr->f = PORT_READ(in_SPR_COMMIT_SR_F [i][j]);
101
102	if (PORT_READ(in_SPR_COMMIT_SR_CY_VAL [i][j]))
103	sr->cy = PORT_READ(in_SPR_COMMIT_SR_CY [i][j]);
104
105	if (PORT_READ(in_SPR_COMMIT_SR_OV_VAL [i][j]))
106	sr->ov = PORT_READ(in_SPR_COMMIT_SR_OV [i][j]);
107	}
108
109	if (PORT_READ(in_SPR_EVENT_VAL [i][j])) // out_SPR_EVENT_ACK [i][j]
110	{
111	SR * sr = static_cast<SR*>(_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_SR]);
112	sr->dsx = PORT_READ(in_SPR_EVENT_SR_DSX [i][j]);
113
114	_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_EPCR]->write(PORT_READ(in_SPR_EVENT_EPCR [i][j]));
115	if (PORT_READ(in_SPR_EVENT_EEAR_WEN [i][j]))
116	_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_EEAR]->write(PORT_READ(in_SPR_EVENT_EEAR [i][j]));
117	if (PORT_READ(in_SPR_EVENT_SR_TO_ESR [i][j]))
118	_spr [i][j][GROUP_SYSTEM_AND_CONTROL][SPR_ESR ]->write(sr->read());
119	}
120	}
121	}
122
123	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
124	end_cycle ();
125	#endif
126
127	log_end(Special_Register_unit,FUNCTION);
128	};
129
130	}; // end namespace special_register_unit
131	}; // end namespace ooo_engine
132	}; // end namespace multi_ooo_engine
133	}; // end namespace core
134
135	}; // end namespace behavioural
136	}; // end namespace morpheo
137	#endif

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