[67] | 1 | #ifdef VHDL |
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| 2 | /* |
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| 3 | * $Id: Queue_vhdl_body.cpp 103 2009-01-16 16:55:32Z moulu $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Generic/Queue/include/Queue.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace generic { |
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| 14 | namespace queue { |
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| 15 | |
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| 16 | |
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| 17 | #undef FUNCTION |
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| 18 | #define FUNCTION "Queue::vhdl_body" |
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| 19 | void Queue::vhdl_body (Vhdl * & vhdl) |
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| 20 | { |
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| 21 | log_printf(FUNC,Queue,FUNCTION,"Begin"); |
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[100] | 22 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 23 | vhdl->set_comment(0," Output"); |
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| 24 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 25 | vhdl->set_body (0,"out_INSERT_ACK <= not signal_FULL;"); |
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| 26 | vhdl->set_body (0,"out_RETIRE_VAL <= not signal_EMPTY;"); |
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| 27 | |
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[67] | 28 | if (_param->_size_queue > 1) |
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[100] | 29 | vhdl->set_body (0,"out_RETIRE_DATA <= reg_DATA(conv_integer(signal_PTR_READ));"); |
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[67] | 30 | else |
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[100] | 31 | vhdl->set_body (0,"out_RETIRE_DATA <= reg_DATA(0);"); |
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[67] | 32 | |
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[100] | 33 | vhdl->set_body (0,""); |
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| 34 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 35 | vhdl->set_comment(0," Slot"); |
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| 36 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 37 | vhdl->set_body (0,""); |
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| 38 | if (_param->_nb_port_slot > 1) |
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| 39 | for (uint32_t i=0; i<_param->_nb_port_slot; ++i) |
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| 40 | if (i==0) |
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| 41 | vhdl->set_body (0,"signal_SLOT_0 <= signal_PTR_READ;"); |
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| 42 | else |
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| 43 | { |
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| 44 | if (is_power2(_param->_size_queue)) |
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| 45 | vhdl->set_body (0,"signal_SLOT_"+toString(i)+" <= signal_PTR_READ+"+std_logic_cst(log2(_param->_size_queue),i)+";"); |
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| 46 | else |
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| 47 | vhdl->set_body (0,"signal_SLOT_"+toString(i)+" <= const_PTR_INIT when signal_SLOT_"+toString(i-1)+" = const_PTR_MAX else signal_SLOT_"+toString(i-1)+"+'1';"); |
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[103] | 48 | |
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[100] | 49 | } |
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| 50 | |
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| 51 | for (uint32_t i=0; i<_param->_nb_port_slot; ++i) |
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| 52 | { |
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| 53 | if (_param->_nb_port_slot > 1) |
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[103] | 54 | vhdl->set_body (0,"signal_SLOT_"+toString(i)+"_VAL <= '1' when reg_NB_ELT > "+std_logic_cst(log2(_param->_size_queue+1),i)+" else '0';"); |
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[100] | 55 | else |
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[103] | 56 | vhdl->set_body (0,"signal_SLOT_"+toString(i)+"_VAL <= not signal_EMPTY;"); |
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[100] | 57 | |
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[103] | 58 | vhdl->set_body (0,"out_SLOT_"+toString(i)+"_VAL <= signal_SLOT_"+toString(i)+"_VAL;"); |
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| 59 | |
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| 60 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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| 61 | std::string str_val_disable=std_logic_cst(_param->_size_data,0)+" when signal_SLOT_"+toString(i)+"_VAL='0' else"; |
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| 62 | #endif |
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[100] | 63 | if (_param->_nb_port_slot > 1) |
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[103] | 64 | { |
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| 65 | vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <= "); |
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| 66 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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| 67 | vhdl->set_body (1,str_val_disable); |
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| 68 | #endif |
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| 69 | vhdl->set_body (1,"reg_DATA(conv_integer(signal_SLOT_"+toString(i)+"));"); |
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| 70 | } |
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[100] | 71 | else |
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| 72 | if (_param->_size_queue > 1) |
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[103] | 73 | { |
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| 74 | vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <="); |
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| 75 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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| 76 | vhdl->set_body (1,str_val_disable); |
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| 77 | #endif |
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| 78 | vhdl->set_body (1,"reg_DATA(conv_integer(signal_PTR_READ));"); |
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| 79 | } |
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[100] | 80 | else |
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[103] | 81 | { |
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| 82 | vhdl->set_body (0,"out_SLOT_"+toString(i)+"_DATA <="); |
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| 83 | #ifdef SYSTEMC_VHDL_COMPATIBILITY |
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| 84 | vhdl->set_body (1,str_val_disable); |
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| 85 | #endif |
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| 86 | vhdl->set_body (1,"reg_DATA(conv_integer(0));"); |
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| 87 | } |
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[100] | 88 | } |
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| 89 | |
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[101] | 90 | if (_param->_have_port_ptr) |
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| 91 | { |
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[100] | 92 | vhdl->set_body (0,""); |
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| 93 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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[101] | 94 | vhdl->set_comment(0," Slot"); |
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| 95 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 96 | vhdl->set_body (0,""); |
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| 97 | if (_param->_have_port_ptr_write) |
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| 98 | vhdl->set_body (0,"out_PTR_WRITE <= signal_PTR_WRITE;"); |
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| 99 | if (_param->_have_port_ptr_read) |
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| 100 | vhdl->set_body (0,"out_PTR_READ <= signal_PTR_READ;"); |
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| 101 | } |
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| 102 | |
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| 103 | vhdl->set_body (0,""); |
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| 104 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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[100] | 105 | vhdl->set_comment(0," Signal"); |
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| 106 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 107 | vhdl->set_body (0,""); |
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| 108 | vhdl->set_body (0,"signal_READ <= (not signal_EMPTY) and in_RETIRE_ACK;"); |
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| 109 | vhdl->set_body (0,"signal_WRITE <= (not signal_FULL ) and in_INSERT_VAL;"); |
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| 110 | vhdl->set_body (0,""); |
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| 111 | if (_param->_nb_port_slot>1) |
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| 112 | { |
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| 113 | vhdl->set_body (0,"signal_EMPTY <= '1' when reg_NB_ELT = "+std_logic_cst(log2(_param->_size_queue+1),0)+" else '0';"); |
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| 114 | if (is_power2(_param->_size_queue)) |
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| 115 | vhdl->set_body (0,"signal_FULL <= reg_NB_ELT "+std_logic_range(log2(_param->_size_queue),log2(_param->_size_queue))+";"); |
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| 116 | else |
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| 117 | vhdl->set_body (0,"signal_FULL <= '1' when reg_NB_ELT = "+std_logic_cst(log2(_param->_size_queue+1),_param->_size_queue)+" else '0';"); |
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| 118 | } |
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| 119 | else |
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| 120 | { |
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| 121 | vhdl->set_body (0,"signal_EMPTY <= reg_EMPTY;"); |
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| 122 | vhdl->set_body (0,"signal_FULL <= reg_FULL ;"); |
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| 123 | } |
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| 124 | vhdl->set_body (0,""); |
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[67] | 125 | if (_param->_size_queue > 1) |
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| 126 | { |
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[100] | 127 | vhdl->set_body (0,"signal_PTR_READ <= reg_PTR_READ;"); |
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| 128 | if (_param->_nb_port_slot>1) |
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| 129 | { |
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| 130 | if (is_power2(_param->_size_queue)) |
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| 131 | vhdl->set_body (0,"signal_PTR_WRITE <= reg_PTR_READ + reg_NB_ELT"+std_logic_range(log2(_param->_size_queue))+";"); |
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| 132 | else |
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| 133 | vhdl->set_body (0,"signal_PTR_WRITE <= reg_PTR_READ + reg_NB_ELT"+std_logic_range(log2(_param->_size_queue))+" when reg_PTR_READ + reg_NB_ELT"+std_logic_range(log2(_param->_size_queue)) +" <= const_PTR_MAX else reg_PTR_READ + reg_NB_ELT"+std_logic_range(log2(_param->_size_queue))+" - const_PTR_MAX-'1';"); |
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[67] | 134 | } |
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| 135 | else |
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[100] | 136 | vhdl->set_body (0,"signal_PTR_WRITE <= reg_PTR_WRITE;"); |
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| 137 | } |
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| 138 | vhdl->set_body (0,""); |
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[67] | 139 | |
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[100] | 140 | if (_param->_nb_port_slot>1) |
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| 141 | { |
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| 142 | vhdl->set_body (0,""); |
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| 143 | vhdl->set_comment(0," nb_elt"); |
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[67] | 144 | if (_param->_size_queue > 1) |
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| 145 | { |
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[100] | 146 | vhdl->set_body (0,"signal_NEXT_NB_ELT <= "); |
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| 147 | vhdl->set_body (1,"reg_NB_ELT when (signal_READ xor signal_WRITE) = '0' else"); |
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| 148 | if (_param->_size_queue > 2) |
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| 149 | { |
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| 150 | vhdl->set_body (1,"reg_NB_ELT +'1' when signal_WRITE='1' else"); |
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| 151 | vhdl->set_body (1,"reg_NB_ELT -'1';"); |
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[67] | 152 | } |
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[100] | 153 | else |
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| 154 | vhdl->set_body (1,"not reg_NB_ELT;"); |
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| 155 | } |
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| 156 | } |
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| 157 | else |
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| 158 | { |
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| 159 | vhdl->set_body (0,"signal_PTR_EQUAL <="); |
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[67] | 160 | if (_param->_size_queue > 1) |
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| 161 | { |
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[100] | 162 | vhdl->set_body (1,"'1' when signal_NEXT_PTR_READ = signal_NEXT_PTR_WRITE else"); |
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| 163 | vhdl->set_body (1,"'0';"); |
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[67] | 164 | } |
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[100] | 165 | else |
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| 166 | vhdl->set_body (1,"'1';"); |
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| 167 | vhdl->set_body (0,"signal_NEXT_FULL <="); |
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| 168 | vhdl->set_body (1,"'1' when signal_WRITE='1' and signal_PTR_EQUAL='1' else"); |
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| 169 | vhdl->set_body (1,"'0' when signal_READ ='1' else"); |
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| 170 | vhdl->set_body (1,"reg_FULL ;"); |
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| 171 | vhdl->set_body (0,"signal_NEXT_EMPTY <="); |
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| 172 | vhdl->set_body (1,"'1' when signal_READ ='1' and signal_PTR_EQUAL='1' else"); |
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| 173 | vhdl->set_body (1,"'0' when signal_WRITE='1' else"); |
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| 174 | vhdl->set_body (1,"reg_EMPTY;"); |
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| 175 | vhdl->set_body (0,""); |
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| 176 | |
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| 177 | vhdl->set_comment(0," write"); |
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[67] | 178 | if (_param->_size_queue > 1) |
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| 179 | { |
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[100] | 180 | vhdl->set_body (0,"signal_NEXT_PTR_WRITE <= "); |
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| 181 | vhdl->set_body (1,"reg_PTR_WRITE when signal_WRITE='0' else"); |
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| 182 | if (is_log2(_param->_size_queue) == false) |
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| 183 | vhdl->set_body (1,"const_PTR_INIT when reg_PTR_WRITE = const_PTR_MAX else"); |
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| 184 | if (_param->_size_queue > 2) |
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| 185 | vhdl->set_body (1,"reg_PTR_WRITE+'1';"); |
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| 186 | else |
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| 187 | vhdl->set_body (1,"not reg_PTR_WRITE;"); |
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[67] | 188 | } |
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[100] | 189 | } |
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| 190 | |
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| 191 | vhdl->set_body (0,""); |
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| 192 | vhdl->set_comment(0," read"); |
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[67] | 193 | if (_param->_size_queue > 1) |
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[100] | 194 | { |
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| 195 | vhdl->set_body (0,"signal_NEXT_PTR_READ <= "); |
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| 196 | vhdl->set_body (1,"reg_PTR_READ when signal_READ='0' else"); |
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| 197 | if (is_log2(_param->_size_queue) == false) |
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| 198 | vhdl->set_body (1,"const_PTR_INIT when reg_PTR_READ = const_PTR_MAX else"); |
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| 199 | |
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| 200 | if (_param->_size_queue > 2) |
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| 201 | vhdl->set_body (1,"reg_PTR_READ +'1';"); |
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| 202 | else |
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| 203 | vhdl->set_body (1,"not reg_PTR_READ;"); |
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| 204 | } |
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| 205 | vhdl->set_body (0,""); |
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| 206 | |
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| 207 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 208 | vhdl->set_comment(0," Registers"); |
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| 209 | vhdl->set_comment(0,"---------------------------------------------------------------------------"); |
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| 210 | vhdl->set_body (0,""); |
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| 211 | vhdl->set_body (0,"queue_write: process (in_CLOCK)"); |
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| 212 | vhdl->set_body (0,"begin -- process queue_write"); |
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| 213 | vhdl->set_body (1,"if in_CLOCK'event and in_CLOCK = '1' then"); |
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| 214 | vhdl->set_body (0,""); |
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| 215 | vhdl->set_body (2,"if (in_NRESET = '0') then"); |
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| 216 | if (_param->_size_queue > 1) |
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[67] | 217 | { |
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[100] | 218 | vhdl->set_body (3,"reg_PTR_READ <= const_PTR_INIT;"); |
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| 219 | if (_param->_nb_port_slot>1) |
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| 220 | vhdl->set_body (3,"reg_NB_ELT <= "+std_logic_cst(log2(_param->_size_queue+1),0)+";"); |
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| 221 | else |
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| 222 | vhdl->set_body (3,"reg_PTR_WRITE <= const_PTR_INIT;"); |
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[67] | 223 | } |
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[100] | 224 | if (_param->_nb_port_slot<=1) |
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| 225 | { |
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| 226 | vhdl->set_body (3,"reg_FULL <= '0';"); |
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| 227 | vhdl->set_body (3,"reg_EMPTY <= '1';"); |
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| 228 | } |
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| 229 | vhdl->set_body (2,"else"); |
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[67] | 230 | if (_param->_size_queue > 1) |
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[100] | 231 | { |
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| 232 | vhdl->set_body (3,"reg_PTR_READ <= signal_NEXT_PTR_READ ;"); |
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| 233 | if (_param->_nb_port_slot>1) |
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| 234 | vhdl->set_body (3,"reg_NB_ELT <= signal_NEXT_NB_ELT ;"); |
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| 235 | else |
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| 236 | vhdl->set_body (3,"reg_PTR_WRITE <= signal_NEXT_PTR_WRITE;"); |
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| 237 | } |
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| 238 | if (_param->_nb_port_slot<=1) |
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| 239 | { |
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| 240 | vhdl->set_body (3,"reg_FULL <= signal_NEXT_FULL ;"); |
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| 241 | vhdl->set_body (3,"reg_EMPTY <= signal_NEXT_EMPTY;"); |
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| 242 | } |
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| 243 | vhdl->set_body (0,""); |
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| 244 | vhdl->set_body (3,"if (signal_WRITE = '1') then"); |
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| 245 | if (_param->_size_queue > 1) |
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| 246 | vhdl->set_body (3,"\treg_DATA(conv_integer(signal_PTR_WRITE)) <= in_INSERT_DATA;"); |
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[67] | 247 | else |
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[100] | 248 | vhdl->set_body (3,"\treg_DATA(0) <= in_INSERT_DATA;"); |
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| 249 | vhdl->set_body (3,"end if;"); |
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| 250 | vhdl->set_body (2,"end if;"); |
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| 251 | vhdl->set_body (0,""); |
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| 252 | vhdl->set_body (1,"end if;"); |
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| 253 | vhdl->set_body (0,"end process queue_write;"); |
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[67] | 254 | |
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| 255 | log_printf(FUNC,Queue,FUNCTION,"End"); |
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| 256 | }; |
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| 257 | |
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| 258 | }; // end namespace queue |
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| 259 | }; // end namespace generic |
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| 260 | |
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| 261 | }; // end namespace behavioural |
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| 262 | }; // end namespace morpheo |
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| 263 | #endif |
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