[2] | 1 | /* |
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| 2 | * $Id$ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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[55] | 9 | #define NB_ITERATION 2 |
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[50] | 10 | |
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[15] | 11 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h" |
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[44] | 12 | #include "Common/include/Test.h" |
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[2] | 13 | |
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| 14 | void test (string name, |
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[55] | 15 | morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param) |
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[2] | 16 | { |
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| 17 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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| 18 | |
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| 19 | try |
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| 20 | { |
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[55] | 21 | cout << _param->print(1); |
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| 22 | _param->test(); |
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[2] | 23 | } |
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| 24 | catch (morpheo::ErrorMorpheo & error) |
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| 25 | { |
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| 26 | cout << "<" << name << "> : " << error.what (); |
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| 27 | return; |
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| 28 | } |
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| 29 | catch (...) |
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| 30 | { |
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| 31 | cerr << "<" << name << "> : This test must generate a error" << endl; |
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| 32 | exit (EXIT_FAILURE); |
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| 33 | } |
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| 34 | |
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[55] | 35 | #ifdef STATISTICS |
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| 36 | morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,1000); |
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| 37 | #endif |
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[50] | 38 | RegisterFile_Monolithic * registerfile = new RegisterFile_Monolithic (name.c_str() |
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[2] | 39 | #ifdef STATISTICS |
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[55] | 40 | ,_param_stat |
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[2] | 41 | #endif |
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[55] | 42 | ,_param); |
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[2] | 43 | |
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| 44 | #ifdef SYSTEMC |
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| 45 | /********************************************************************* |
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| 46 | * Déclarations des signaux |
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| 47 | *********************************************************************/ |
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| 48 | sc_clock CLOCK ("clock", 1.0, 0.5); |
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[6] | 49 | sc_signal<Tcontrol_t> NRESET; |
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[2] | 50 | |
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[55] | 51 | sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read]; |
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| 52 | sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read]; |
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| 53 | sc_signal<Taddress_t> READ_ADDRESS [_param->_nb_port_read]; |
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| 54 | sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read]; |
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[2] | 55 | |
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[55] | 56 | sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write]; |
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| 57 | sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write]; |
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| 58 | sc_signal<Taddress_t> WRITE_ADDRESS [_param->_nb_port_write]; |
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| 59 | sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write]; |
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[2] | 60 | |
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[55] | 61 | sc_signal<Tcontrol_t> READ_WRITE_VAL [_param->_nb_port_read_write]; |
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| 62 | sc_signal<Tcontrol_t> READ_WRITE_ACK [_param->_nb_port_read_write]; |
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| 63 | sc_signal<Tcontrol_t> READ_WRITE_RW [_param->_nb_port_read_write]; |
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| 64 | sc_signal<Taddress_t> READ_WRITE_ADDRESS [_param->_nb_port_read_write]; |
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| 65 | sc_signal<Tdata_t> READ_WRITE_RDATA [_param->_nb_port_read_write]; |
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| 66 | sc_signal<Tdata_t> READ_WRITE_WDATA [_param->_nb_port_read_write]; |
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| 67 | |
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[2] | 68 | /******************************************************** |
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| 69 | * Instanciation |
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| 70 | ********************************************************/ |
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| 71 | |
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[15] | 72 | cout << "<" << name << "> Instanciation of registerfile" << endl; |
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[2] | 73 | |
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| 74 | (*(registerfile->in_CLOCK)) (CLOCK); |
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[6] | 75 | (*(registerfile->in_NRESET)) (NRESET); |
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[2] | 76 | |
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[55] | 77 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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[2] | 78 | { |
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[6] | 79 | (*(registerfile-> in_READ_VAL [i])) (READ_VAL [i]); |
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| 80 | (*(registerfile->out_READ_ACK [i])) (READ_ACK [i]); |
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[2] | 81 | (*(registerfile-> in_READ_ADDRESS [i])) (READ_ADDRESS [i]); |
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| 82 | (*(registerfile->out_READ_DATA [i])) (READ_DATA [i]); |
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| 83 | } |
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[55] | 84 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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[2] | 85 | { |
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[6] | 86 | (*(registerfile-> in_WRITE_VAL [i])) (WRITE_VAL [i]); |
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| 87 | (*(registerfile->out_WRITE_ACK [i])) (WRITE_ACK [i]); |
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[2] | 88 | (*(registerfile-> in_WRITE_ADDRESS [i])) (WRITE_ADDRESS [i]); |
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| 89 | (*(registerfile-> in_WRITE_DATA [i])) (WRITE_DATA [i]); |
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| 90 | } |
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[55] | 91 | for (uint32_t i=0; i<_param->_nb_port_read_write; i++) |
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| 92 | { |
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| 93 | (*(registerfile-> in_READ_WRITE_VAL [i])) (READ_WRITE_VAL [i]); |
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| 94 | (*(registerfile->out_READ_WRITE_ACK [i])) (READ_WRITE_ACK [i]); |
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| 95 | (*(registerfile-> in_READ_WRITE_RW [i])) (READ_WRITE_RW [i]); |
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| 96 | (*(registerfile-> in_READ_WRITE_ADDRESS [i])) (READ_WRITE_ADDRESS [i]); |
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| 97 | (*(registerfile-> in_READ_WRITE_WDATA [i])) (READ_WRITE_WDATA [i]); |
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| 98 | (*(registerfile->out_READ_WRITE_RDATA [i])) (READ_WRITE_RDATA [i]); |
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| 99 | } |
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[2] | 100 | |
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[50] | 101 | cout << "<" << name << "> Start Simulation ............" << endl; |
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| 102 | Time * _time = new Time(); |
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| 103 | |
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[2] | 104 | /******************************************************** |
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| 105 | * Simulation - Begin |
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| 106 | ********************************************************/ |
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| 107 | |
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| 108 | // Initialisation |
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| 109 | |
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| 110 | sc_start(0); |
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| 111 | |
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[55] | 112 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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[6] | 113 | WRITE_VAL [i] .write (0); |
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[55] | 114 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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[6] | 115 | READ_VAL [i] .write (0); |
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[55] | 116 | for (uint32_t i=0; i<_param->_nb_port_read_write; i++) |
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| 117 | READ_WRITE_VAL [i] .write (0); |
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[2] | 118 | |
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[42] | 119 | NRESET.write(0); |
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| 120 | |
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[2] | 121 | sc_start(5); |
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| 122 | |
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[42] | 123 | NRESET.write(1); |
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| 124 | |
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[2] | 125 | |
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[50] | 126 | for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++) |
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| 127 | { |
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| 128 | cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl; |
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[2] | 129 | |
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[50] | 130 | // random init |
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| 131 | uint32_t grain = 0; |
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| 132 | //uint32_t grain = static_cast<uint32_t>(time(NULL)); |
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[2] | 133 | |
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[50] | 134 | srand(grain); |
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[2] | 135 | |
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[55] | 136 | Tdata_t tab [_param->_nb_word]; |
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[50] | 137 | |
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[55] | 138 | for (uint32_t i=0; i<_param->_nb_word; i++) |
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| 139 | tab[i]= rand()%(1<<(_param->_size_word-1)); |
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[50] | 140 | |
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| 141 | Taddress_t address_next = 0; |
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| 142 | Taddress_t nb_ack = 0; |
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| 143 | |
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[55] | 144 | while (nb_ack < _param->_nb_word) |
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[2] | 145 | { |
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[50] | 146 | cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; |
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[2] | 147 | |
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[55] | 148 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
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[50] | 149 | { |
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[55] | 150 | if ((address_next < _param->_nb_word) and |
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[50] | 151 | (WRITE_VAL [num_port].read() == 0)) |
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| 152 | { |
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| 153 | cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl; |
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| 154 | |
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| 155 | WRITE_VAL [num_port] .write(1); |
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| 156 | WRITE_DATA [num_port] .write(tab[address_next]); |
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| 157 | WRITE_ADDRESS [num_port] .write(address_next++); |
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| 158 | |
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| 159 | // Address can be not a multiple of nb_port_write |
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[55] | 160 | if (address_next >= _param->_nb_word) |
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[50] | 161 | break; |
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| 162 | } |
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| 163 | } |
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[55] | 164 | |
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| 165 | for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) |
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| 166 | { |
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| 167 | if ((address_next < _param->_nb_word) and |
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| 168 | (READ_WRITE_VAL [num_port].read() == 0)) |
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| 169 | { |
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| 170 | cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl; |
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| 171 | |
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| 172 | READ_WRITE_VAL [num_port] .write(1); |
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| 173 | READ_WRITE_RW [num_port] .write(RW_WRITE); |
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| 174 | READ_WRITE_WDATA [num_port] .write(tab[address_next]); |
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| 175 | READ_WRITE_ADDRESS [num_port] .write(address_next++); |
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| 176 | |
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| 177 | // Address can be not a multiple of nb_port_write |
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| 178 | if (address_next >= _param->_nb_word) |
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| 179 | break; |
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| 180 | } |
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| 181 | } |
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[50] | 182 | |
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| 183 | sc_start(1); |
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[2] | 184 | |
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[50] | 185 | // reset write_val port |
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[55] | 186 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
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[50] | 187 | { |
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| 188 | if ((WRITE_ACK [num_port].read() == 1) and |
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| 189 | (WRITE_VAL [num_port].read() == 1)) |
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| 190 | { |
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| 191 | WRITE_VAL [num_port] .write(0); |
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| 192 | nb_ack ++; |
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| 193 | } |
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| 194 | } |
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[55] | 195 | // reset write_val port |
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| 196 | for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) |
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| 197 | { |
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| 198 | if ((READ_WRITE_ACK [num_port].read() == 1) and |
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| 199 | (READ_WRITE_VAL [num_port].read() == 1)) |
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| 200 | { |
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| 201 | READ_WRITE_VAL [num_port] .write(0); |
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| 202 | nb_ack ++; |
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| 203 | } |
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| 204 | } |
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[2] | 205 | |
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[50] | 206 | sc_start(0); |
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[2] | 207 | } |
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[50] | 208 | |
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| 209 | address_next = 0; |
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| 210 | nb_ack = 0; |
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[2] | 211 | |
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[50] | 212 | cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl; |
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| 213 | |
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[55] | 214 | Tdata_t read_address [_param->_nb_port_read]; |
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| 215 | Tdata_t read_write_address [_param->_nb_port_read_write]; |
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[2] | 216 | |
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[55] | 217 | while (nb_ack < _param->_nb_word) |
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[50] | 218 | { |
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| 219 | cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; |
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| 220 | |
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[55] | 221 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
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[50] | 222 | { |
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[55] | 223 | if ((address_next < _param->_nb_word) and |
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[50] | 224 | (READ_VAL [num_port].read() == 0)) |
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| 225 | { |
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| 226 | read_address [num_port] = address_next++; |
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[2] | 227 | |
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[50] | 228 | READ_VAL [num_port].write(1); |
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| 229 | READ_ADDRESS [num_port].write(read_address [num_port]); |
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[2] | 230 | |
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[55] | 231 | if (address_next >= _param->_nb_word) |
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[50] | 232 | break; |
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| 233 | } |
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| 234 | } |
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[2] | 235 | |
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[55] | 236 | for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) |
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| 237 | { |
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| 238 | if ((address_next < _param->_nb_word) and |
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| 239 | (READ_WRITE_VAL [num_port].read() == 0)) |
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| 240 | { |
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| 241 | read_write_address [num_port] = address_next++; |
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| 242 | |
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| 243 | READ_WRITE_VAL [num_port].write(1); |
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| 244 | READ_WRITE_RW [num_port].write(RW_READ); |
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| 245 | READ_WRITE_ADDRESS [num_port].write(read_write_address [num_port]); |
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| 246 | |
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| 247 | if (address_next >= _param->_nb_word) |
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| 248 | break; |
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| 249 | } |
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| 250 | } |
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| 251 | |
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| 252 | |
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[50] | 253 | sc_start(1); |
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[2] | 254 | |
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[50] | 255 | // reset write_val port |
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[55] | 256 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
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[50] | 257 | { |
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| 258 | if ((READ_ACK [num_port].read() == 1) and |
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| 259 | (READ_VAL [num_port].read() == 1)) |
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| 260 | { |
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| 261 | READ_VAL [num_port] .write(0); |
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[2] | 262 | |
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[50] | 263 | cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl; |
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[2] | 264 | |
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[50] | 265 | TEST(Tdata_t,READ_DATA [num_port].read(), tab[read_address [num_port]]); |
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| 266 | nb_ack ++; |
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| 267 | } |
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| 268 | } |
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[2] | 269 | |
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[55] | 270 | for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) |
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| 271 | { |
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| 272 | if ((READ_WRITE_ACK [num_port].read() == 1) and |
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| 273 | (READ_WRITE_VAL [num_port].read() == 1)) |
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| 274 | { |
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| 275 | READ_WRITE_VAL [num_port] .write(0); |
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| 276 | |
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| 277 | cout << "(" << num_port << ") [" << read_write_address [num_port] << "] => " << READ_WRITE_RDATA [num_port].read() << endl; |
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| 278 | |
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| 279 | TEST(Tdata_t,READ_WRITE_RDATA [num_port].read(), tab[read_write_address [num_port]]); |
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| 280 | nb_ack ++; |
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| 281 | } |
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| 282 | } |
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| 283 | |
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[50] | 284 | sc_start(0); |
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[2] | 285 | } |
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| 286 | } |
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| 287 | |
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| 288 | /******************************************************** |
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| 289 | * Simulation - End |
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| 290 | ********************************************************/ |
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| 291 | |
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[50] | 292 | TEST_STR(bool,true,true, "End of Simulation"); |
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| 293 | delete _time; |
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[2] | 294 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
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| 295 | |
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| 296 | #endif |
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| 297 | |
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| 298 | delete registerfile; |
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| 299 | } |
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