[2] | 1 | /* |
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| 2 | * $Id$ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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[57] | 9 | #define NB_ITERATION 1 |
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[50] | 10 | |
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[15] | 11 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h" |
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[44] | 12 | #include "Common/include/Test.h" |
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[2] | 13 | |
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| 14 | void test (string name, |
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[55] | 15 | morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param) |
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[2] | 16 | { |
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| 17 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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| 18 | |
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| 19 | try |
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| 20 | { |
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[55] | 21 | cout << _param->print(1); |
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| 22 | _param->test(); |
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[2] | 23 | } |
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| 24 | catch (morpheo::ErrorMorpheo & error) |
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| 25 | { |
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| 26 | cout << "<" << name << "> : " << error.what (); |
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| 27 | return; |
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| 28 | } |
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| 29 | catch (...) |
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| 30 | { |
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| 31 | cerr << "<" << name << "> : This test must generate a error" << endl; |
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| 32 | exit (EXIT_FAILURE); |
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| 33 | } |
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| 34 | |
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[55] | 35 | #ifdef STATISTICS |
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[71] | 36 | morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,100); |
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[55] | 37 | #endif |
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[50] | 38 | RegisterFile_Monolithic * registerfile = new RegisterFile_Monolithic (name.c_str() |
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[2] | 39 | #ifdef STATISTICS |
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[55] | 40 | ,_param_stat |
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[2] | 41 | #endif |
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[55] | 42 | ,_param); |
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[2] | 43 | |
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| 44 | #ifdef SYSTEMC |
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| 45 | /********************************************************************* |
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| 46 | * Déclarations des signaux |
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| 47 | *********************************************************************/ |
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| 48 | sc_clock CLOCK ("clock", 1.0, 0.5); |
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[6] | 49 | sc_signal<Tcontrol_t> NRESET; |
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[2] | 50 | |
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[55] | 51 | sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read]; |
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| 52 | sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read]; |
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| 53 | sc_signal<Taddress_t> READ_ADDRESS [_param->_nb_port_read]; |
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| 54 | sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read]; |
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[2] | 55 | |
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[55] | 56 | sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write]; |
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| 57 | sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write]; |
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| 58 | sc_signal<Taddress_t> WRITE_ADDRESS [_param->_nb_port_write]; |
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| 59 | sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write]; |
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[2] | 60 | |
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[55] | 61 | sc_signal<Tcontrol_t> READ_WRITE_VAL [_param->_nb_port_read_write]; |
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| 62 | sc_signal<Tcontrol_t> READ_WRITE_ACK [_param->_nb_port_read_write]; |
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| 63 | sc_signal<Tcontrol_t> READ_WRITE_RW [_param->_nb_port_read_write]; |
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| 64 | sc_signal<Taddress_t> READ_WRITE_ADDRESS [_param->_nb_port_read_write]; |
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| 65 | sc_signal<Tdata_t> READ_WRITE_RDATA [_param->_nb_port_read_write]; |
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| 66 | sc_signal<Tdata_t> READ_WRITE_WDATA [_param->_nb_port_read_write]; |
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| 67 | |
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[2] | 68 | /******************************************************** |
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| 69 | * Instanciation |
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| 70 | ********************************************************/ |
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| 71 | |
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[15] | 72 | cout << "<" << name << "> Instanciation of registerfile" << endl; |
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[2] | 73 | |
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| 74 | (*(registerfile->in_CLOCK)) (CLOCK); |
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[6] | 75 | (*(registerfile->in_NRESET)) (NRESET); |
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[2] | 76 | |
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[55] | 77 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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[2] | 78 | { |
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[6] | 79 | (*(registerfile-> in_READ_VAL [i])) (READ_VAL [i]); |
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| 80 | (*(registerfile->out_READ_ACK [i])) (READ_ACK [i]); |
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[62] | 81 | if (_param->_have_port_address) |
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[2] | 82 | (*(registerfile-> in_READ_ADDRESS [i])) (READ_ADDRESS [i]); |
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| 83 | (*(registerfile->out_READ_DATA [i])) (READ_DATA [i]); |
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| 84 | } |
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[55] | 85 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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[2] | 86 | { |
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[6] | 87 | (*(registerfile-> in_WRITE_VAL [i])) (WRITE_VAL [i]); |
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| 88 | (*(registerfile->out_WRITE_ACK [i])) (WRITE_ACK [i]); |
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[62] | 89 | if (_param->_have_port_address) |
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[2] | 90 | (*(registerfile-> in_WRITE_ADDRESS [i])) (WRITE_ADDRESS [i]); |
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| 91 | (*(registerfile-> in_WRITE_DATA [i])) (WRITE_DATA [i]); |
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| 92 | } |
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[55] | 93 | for (uint32_t i=0; i<_param->_nb_port_read_write; i++) |
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| 94 | { |
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| 95 | (*(registerfile-> in_READ_WRITE_VAL [i])) (READ_WRITE_VAL [i]); |
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| 96 | (*(registerfile->out_READ_WRITE_ACK [i])) (READ_WRITE_ACK [i]); |
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| 97 | (*(registerfile-> in_READ_WRITE_RW [i])) (READ_WRITE_RW [i]); |
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[62] | 98 | if (_param->_have_port_address) |
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[55] | 99 | (*(registerfile-> in_READ_WRITE_ADDRESS [i])) (READ_WRITE_ADDRESS [i]); |
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| 100 | (*(registerfile-> in_READ_WRITE_WDATA [i])) (READ_WRITE_WDATA [i]); |
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| 101 | (*(registerfile->out_READ_WRITE_RDATA [i])) (READ_WRITE_RDATA [i]); |
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| 102 | } |
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[2] | 103 | |
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[50] | 104 | cout << "<" << name << "> Start Simulation ............" << endl; |
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| 105 | Time * _time = new Time(); |
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| 106 | |
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[2] | 107 | /******************************************************** |
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| 108 | * Simulation - Begin |
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| 109 | ********************************************************/ |
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| 110 | |
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| 111 | // Initialisation |
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| 112 | |
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| 113 | sc_start(0); |
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| 114 | |
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[55] | 115 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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[6] | 116 | WRITE_VAL [i] .write (0); |
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[55] | 117 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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[6] | 118 | READ_VAL [i] .write (0); |
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[55] | 119 | for (uint32_t i=0; i<_param->_nb_port_read_write; i++) |
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| 120 | READ_WRITE_VAL [i] .write (0); |
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[2] | 121 | |
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[42] | 122 | NRESET.write(0); |
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| 123 | |
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[2] | 124 | sc_start(5); |
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| 125 | |
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[42] | 126 | NRESET.write(1); |
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| 127 | |
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[2] | 128 | |
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[50] | 129 | for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++) |
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| 130 | { |
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| 131 | cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl; |
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[2] | 132 | |
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[50] | 133 | // random init |
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| 134 | uint32_t grain = 0; |
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| 135 | //uint32_t grain = static_cast<uint32_t>(time(NULL)); |
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[2] | 136 | |
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[50] | 137 | srand(grain); |
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[2] | 138 | |
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[55] | 139 | Tdata_t tab [_param->_nb_word]; |
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[50] | 140 | |
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[55] | 141 | for (uint32_t i=0; i<_param->_nb_word; i++) |
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| 142 | tab[i]= rand()%(1<<(_param->_size_word-1)); |
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[50] | 143 | |
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| 144 | Taddress_t address_next = 0; |
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| 145 | Taddress_t nb_ack = 0; |
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| 146 | |
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[55] | 147 | while (nb_ack < _param->_nb_word) |
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[2] | 148 | { |
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[50] | 149 | cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; |
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[2] | 150 | |
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[55] | 151 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
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[50] | 152 | { |
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[55] | 153 | if ((address_next < _param->_nb_word) and |
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[50] | 154 | (WRITE_VAL [num_port].read() == 0)) |
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| 155 | { |
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| 156 | cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl; |
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| 157 | |
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| 158 | WRITE_VAL [num_port] .write(1); |
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| 159 | WRITE_DATA [num_port] .write(tab[address_next]); |
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| 160 | WRITE_ADDRESS [num_port] .write(address_next++); |
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| 161 | |
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| 162 | // Address can be not a multiple of nb_port_write |
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[55] | 163 | if (address_next >= _param->_nb_word) |
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[50] | 164 | break; |
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| 165 | } |
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| 166 | } |
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[55] | 167 | |
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| 168 | for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) |
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| 169 | { |
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| 170 | if ((address_next < _param->_nb_word) and |
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| 171 | (READ_WRITE_VAL [num_port].read() == 0)) |
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| 172 | { |
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| 173 | cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl; |
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| 174 | |
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| 175 | READ_WRITE_VAL [num_port] .write(1); |
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| 176 | READ_WRITE_RW [num_port] .write(RW_WRITE); |
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| 177 | READ_WRITE_WDATA [num_port] .write(tab[address_next]); |
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| 178 | READ_WRITE_ADDRESS [num_port] .write(address_next++); |
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| 179 | |
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| 180 | // Address can be not a multiple of nb_port_write |
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| 181 | if (address_next >= _param->_nb_word) |
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| 182 | break; |
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| 183 | } |
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| 184 | } |
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[50] | 185 | |
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| 186 | sc_start(1); |
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[2] | 187 | |
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[50] | 188 | // reset write_val port |
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[55] | 189 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
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[50] | 190 | { |
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| 191 | if ((WRITE_ACK [num_port].read() == 1) and |
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| 192 | (WRITE_VAL [num_port].read() == 1)) |
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| 193 | { |
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| 194 | WRITE_VAL [num_port] .write(0); |
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| 195 | nb_ack ++; |
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| 196 | } |
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| 197 | } |
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[55] | 198 | // reset write_val port |
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| 199 | for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) |
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| 200 | { |
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| 201 | if ((READ_WRITE_ACK [num_port].read() == 1) and |
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| 202 | (READ_WRITE_VAL [num_port].read() == 1)) |
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| 203 | { |
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| 204 | READ_WRITE_VAL [num_port] .write(0); |
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| 205 | nb_ack ++; |
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| 206 | } |
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| 207 | } |
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[2] | 208 | |
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[50] | 209 | sc_start(0); |
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[2] | 210 | } |
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[50] | 211 | |
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| 212 | address_next = 0; |
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| 213 | nb_ack = 0; |
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[2] | 214 | |
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[50] | 215 | cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl; |
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| 216 | |
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[55] | 217 | Tdata_t read_address [_param->_nb_port_read]; |
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| 218 | Tdata_t read_write_address [_param->_nb_port_read_write]; |
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[2] | 219 | |
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[55] | 220 | while (nb_ack < _param->_nb_word) |
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[50] | 221 | { |
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| 222 | cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; |
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| 223 | |
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[55] | 224 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
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[50] | 225 | { |
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[55] | 226 | if ((address_next < _param->_nb_word) and |
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[50] | 227 | (READ_VAL [num_port].read() == 0)) |
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| 228 | { |
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| 229 | read_address [num_port] = address_next++; |
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[2] | 230 | |
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[50] | 231 | READ_VAL [num_port].write(1); |
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| 232 | READ_ADDRESS [num_port].write(read_address [num_port]); |
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[2] | 233 | |
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[55] | 234 | if (address_next >= _param->_nb_word) |
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[50] | 235 | break; |
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| 236 | } |
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| 237 | } |
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[2] | 238 | |
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[55] | 239 | for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) |
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| 240 | { |
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| 241 | if ((address_next < _param->_nb_word) and |
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| 242 | (READ_WRITE_VAL [num_port].read() == 0)) |
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| 243 | { |
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| 244 | read_write_address [num_port] = address_next++; |
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| 245 | |
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| 246 | READ_WRITE_VAL [num_port].write(1); |
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| 247 | READ_WRITE_RW [num_port].write(RW_READ); |
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| 248 | READ_WRITE_ADDRESS [num_port].write(read_write_address [num_port]); |
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| 249 | |
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| 250 | if (address_next >= _param->_nb_word) |
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| 251 | break; |
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| 252 | } |
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| 253 | } |
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| 254 | |
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| 255 | |
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[50] | 256 | sc_start(1); |
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[2] | 257 | |
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[50] | 258 | // reset write_val port |
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[55] | 259 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
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[50] | 260 | { |
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| 261 | if ((READ_ACK [num_port].read() == 1) and |
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| 262 | (READ_VAL [num_port].read() == 1)) |
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| 263 | { |
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| 264 | READ_VAL [num_port] .write(0); |
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[2] | 265 | |
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[50] | 266 | cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl; |
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[2] | 267 | |
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[50] | 268 | TEST(Tdata_t,READ_DATA [num_port].read(), tab[read_address [num_port]]); |
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| 269 | nb_ack ++; |
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| 270 | } |
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| 271 | } |
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[2] | 272 | |
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[55] | 273 | for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) |
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| 274 | { |
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| 275 | if ((READ_WRITE_ACK [num_port].read() == 1) and |
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| 276 | (READ_WRITE_VAL [num_port].read() == 1)) |
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| 277 | { |
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| 278 | READ_WRITE_VAL [num_port] .write(0); |
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| 279 | |
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| 280 | cout << "(" << num_port << ") [" << read_write_address [num_port] << "] => " << READ_WRITE_RDATA [num_port].read() << endl; |
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| 281 | |
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| 282 | TEST(Tdata_t,READ_WRITE_RDATA [num_port].read(), tab[read_write_address [num_port]]); |
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| 283 | nb_ack ++; |
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| 284 | } |
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| 285 | } |
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| 286 | |
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[50] | 287 | sc_start(0); |
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[2] | 288 | } |
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| 289 | } |
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| 290 | |
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| 291 | /******************************************************** |
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| 292 | * Simulation - End |
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| 293 | ********************************************************/ |
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| 294 | |
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[50] | 295 | TEST_STR(bool,true,true, "End of Simulation"); |
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| 296 | delete _time; |
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[2] | 297 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
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| 298 | |
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| 299 | #endif |
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| 300 | |
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| 301 | delete registerfile; |
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| 302 | } |
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