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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 16 years ago
Almost complete design with Test and test platform
Property svn:keywords set to `Id`
File size: 10.1 KB

Rev	Line
[2]	1	/*
	2	* $Id: test.cpp 88 2008-12-10 18:31:39Z rosiere $
	3	*
	4	* [ Description ]
	5	*
	6	* Test
	7	*/
	8
[78]	9	#define NB_ITERATION 16
[82]	10	#define CYCLE_MAX 1024*NB_ITERATION
[15]	11	#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h"
[44]	12	#include "Common/include/Test.h"
[2]	13
	14	void test (string name,
[55]	15	morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param)
[2]	16	{
	17	cout << "<" << name << "> : Simulation SystemC" << endl;
	18
	19	try
	20	{
[55]	21	cout << _param->print(1);
	22	_param->test();
[2]	23	}
	24	catch (morpheo::ErrorMorpheo & error)
	25	{
	26	cout << "<" << name << "> : " << error.what ();
	27	return;
	28	}
	29	catch (...)
	30	{
	31	cerr << "<" << name << "> : This test must generate a error" << endl;
	32	exit (EXIT_FAILURE);
	33	}
	34
[88]	35	Tusage_t _usage = USE_ALL;
	36
	37	// _usage = usage_unset(_usage,USE_SYSTEMC );
	38	// _usage = usage_unset(_usage,USE_VHDL );
	39	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
	40	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
	41	// _usage = usage_unset(_usage,USE_POSITION );
	42	// _usage = usage_unset(_usage,USE_STATISTICS );
	43	// _usage = usage_unset(_usage,USE_INFORMATION );
	44
[55]	45	#ifdef STATISTICS
[71]	46	morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,100);
[55]	47	#endif
[82]	48	RegisterFile_Monolithic * registerfile = new RegisterFile_Monolithic
	49	(name.c_str()
[2]	50	#ifdef STATISTICS
[82]	51	,_param_stat
[2]	52	#endif
[82]	53	,_param
[88]	54	,_usage);
[2]	55
	56	#ifdef SYSTEMC
	57	/*********************************************************************
	58	* Déclarations des signaux
	59	*********************************************************************/
	60	sc_clock CLOCK ("clock", 1.0, 0.5);
[6]	61	sc_signal<Tcontrol_t> NRESET;
[2]	62
[55]	63	sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read];
	64	sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read];
	65	sc_signal<Taddress_t> READ_ADDRESS [_param->_nb_port_read];
	66	sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read];
[2]	67
[55]	68	sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write];
	69	sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write];
	70	sc_signal<Taddress_t> WRITE_ADDRESS [_param->_nb_port_write];
	71	sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write];
[2]	72
[55]	73	sc_signal<Tcontrol_t> READ_WRITE_VAL [_param->_nb_port_read_write];
	74	sc_signal<Tcontrol_t> READ_WRITE_ACK [_param->_nb_port_read_write];
	75	sc_signal<Tcontrol_t> READ_WRITE_RW [_param->_nb_port_read_write];
	76	sc_signal<Taddress_t> READ_WRITE_ADDRESS [_param->_nb_port_read_write];
	77	sc_signal<Tdata_t> READ_WRITE_RDATA [_param->_nb_port_read_write];
	78	sc_signal<Tdata_t> READ_WRITE_WDATA [_param->_nb_port_read_write];
	79
[2]	80	/********************************************************
	81	* Instanciation
	82	********************************************************/
	83
[15]	84	cout << "<" << name << "> Instanciation of registerfile" << endl;
[2]	85
	86	(*(registerfile->in_CLOCK)) (CLOCK);
[6]	87	(*(registerfile->in_NRESET)) (NRESET);
[2]	88
[55]	89	for (uint32_t i=0; i<_param->_nb_port_read; i++)
[2]	90	{
[6]	91	(*(registerfile-> in_READ_VAL [i])) (READ_VAL [i]);
	92	(*(registerfile->out_READ_ACK [i])) (READ_ACK [i]);
[62]	93	if (_param->_have_port_address)
[2]	94	(*(registerfile-> in_READ_ADDRESS [i])) (READ_ADDRESS [i]);
	95	(*(registerfile->out_READ_DATA [i])) (READ_DATA [i]);
	96	}
[55]	97	for (uint32_t i=0; i<_param->_nb_port_write; i++)
[2]	98	{
[6]	99	(*(registerfile-> in_WRITE_VAL [i])) (WRITE_VAL [i]);
	100	(*(registerfile->out_WRITE_ACK [i])) (WRITE_ACK [i]);
[62]	101	if (_param->_have_port_address)
[2]	102	(*(registerfile-> in_WRITE_ADDRESS [i])) (WRITE_ADDRESS [i]);
	103	(*(registerfile-> in_WRITE_DATA [i])) (WRITE_DATA [i]);
	104	}
[55]	105	for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
	106	{
	107	(*(registerfile-> in_READ_WRITE_VAL [i])) (READ_WRITE_VAL [i]);
	108	(*(registerfile->out_READ_WRITE_ACK [i])) (READ_WRITE_ACK [i]);
	109	(*(registerfile-> in_READ_WRITE_RW [i])) (READ_WRITE_RW [i]);
[62]	110	if (_param->_have_port_address)
[55]	111	(*(registerfile-> in_READ_WRITE_ADDRESS [i])) (READ_WRITE_ADDRESS [i]);
	112	(*(registerfile-> in_READ_WRITE_WDATA [i])) (READ_WRITE_WDATA [i]);
	113	(*(registerfile->out_READ_WRITE_RDATA [i])) (READ_WRITE_RDATA [i]);
	114	}
[2]	115
[50]	116	cout << "<" << name << "> Start Simulation ............" << endl;
	117	Time * _time = new Time();
	118
[2]	119	/********************************************************
	120	* Simulation - Begin
	121	********************************************************/
	122
	123	// Initialisation
	124
	125	sc_start(0);
	126
[55]	127	for (uint32_t i=0; i<_param->_nb_port_write; i++)
[6]	128	WRITE_VAL [i] .write (0);
[55]	129	for (uint32_t i=0; i<_param->_nb_port_read; i++)
[6]	130	READ_VAL [i] .write (0);
[55]	131	for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
	132	READ_WRITE_VAL [i] .write (0);
[2]	133
[42]	134	NRESET.write(0);
	135
[2]	136	sc_start(5);
	137
[42]	138	NRESET.write(1);
	139
[2]	140
[50]	141	for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++)
	142	{
	143	cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl;
[2]	144
[50]	145	// random init
	146	uint32_t grain = 0;
	147	//uint32_t grain = static_cast<uint32_t>(time(NULL));
[2]	148
[50]	149	srand(grain);
[2]	150
[55]	151	Tdata_t tab [_param->_nb_word];
[50]	152
[55]	153	for (uint32_t i=0; i<_param->_nb_word; i++)
	154	tab[i]= rand()%(1<<(_param->_size_word-1));
[50]	155
	156	Taddress_t address_next = 0;
	157	Taddress_t nb_ack = 0;
	158
[55]	159	while (nb_ack < _param->_nb_word)
[2]	160	{
[50]	161	cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl;
[2]	162
[55]	163	for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++)
[50]	164	{
[55]	165	if ((address_next < _param->_nb_word) and
[50]	166	(WRITE_VAL [num_port].read() == 0))
	167	{
	168	cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl;
	169
	170	WRITE_VAL [num_port] .write(1);
	171	WRITE_DATA [num_port] .write(tab[address_next]);
	172	WRITE_ADDRESS [num_port] .write(address_next++);
	173
	174	// Address can be not a multiple of nb_port_write
[55]	175	if (address_next >= _param->_nb_word)
[50]	176	break;
	177	}
	178	}
[55]	179
	180	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
	181	{
	182	if ((address_next < _param->_nb_word) and
	183	(READ_WRITE_VAL [num_port].read() == 0))
	184	{
	185	cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl;
	186
	187	READ_WRITE_VAL [num_port] .write(1);
	188	READ_WRITE_RW [num_port] .write(RW_WRITE);
	189	READ_WRITE_WDATA [num_port] .write(tab[address_next]);
	190	READ_WRITE_ADDRESS [num_port] .write(address_next++);
	191
	192	// Address can be not a multiple of nb_port_write
	193	if (address_next >= _param->_nb_word)
	194	break;
	195	}
	196	}
[50]	197
	198	sc_start(1);
[2]	199
[50]	200	// reset write_val port
[55]	201	for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++)
[50]	202	{
	203	if ((WRITE_ACK [num_port].read() == 1) and
	204	(WRITE_VAL [num_port].read() == 1))
	205	{
	206	WRITE_VAL [num_port] .write(0);
	207	nb_ack ++;
	208	}
	209	}
[55]	210	// reset write_val port
	211	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
	212	{
	213	if ((READ_WRITE_ACK [num_port].read() == 1) and
	214	(READ_WRITE_VAL [num_port].read() == 1))
	215	{
	216	READ_WRITE_VAL [num_port] .write(0);
	217	nb_ack ++;
	218	}
	219	}
[2]	220
[50]	221	sc_start(0);
[2]	222	}
[50]	223
	224	address_next = 0;
	225	nb_ack = 0;
[2]	226
[50]	227	cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl;
	228
[55]	229	Tdata_t read_address [_param->_nb_port_read];
	230	Tdata_t read_write_address [_param->_nb_port_read_write];
[2]	231
[55]	232	while (nb_ack < _param->_nb_word)
[50]	233	{
	234	cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl;
	235
[55]	236	for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
[50]	237	{
[55]	238	if ((address_next < _param->_nb_word) and
[50]	239	(READ_VAL [num_port].read() == 0))
	240	{
	241	read_address [num_port] = address_next++;
[2]	242
[50]	243	READ_VAL [num_port].write(1);
	244	READ_ADDRESS [num_port].write(read_address [num_port]);
[2]	245
[55]	246	if (address_next >= _param->_nb_word)
[50]	247	break;
	248	}
	249	}
[2]	250
[55]	251	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
	252	{
	253	if ((address_next < _param->_nb_word) and
	254	(READ_WRITE_VAL [num_port].read() == 0))
	255	{
	256	read_write_address [num_port] = address_next++;
	257
	258	READ_WRITE_VAL [num_port].write(1);
	259	READ_WRITE_RW [num_port].write(RW_READ);
	260	READ_WRITE_ADDRESS [num_port].write(read_write_address [num_port]);
	261
	262	if (address_next >= _param->_nb_word)
	263	break;
	264	}
	265	}
	266
	267
[50]	268	sc_start(1);
[2]	269
[50]	270	// reset write_val port
[55]	271	for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
[50]	272	{
	273	if ((READ_ACK [num_port].read() == 1) and
	274	(READ_VAL [num_port].read() == 1))
	275	{
	276	READ_VAL [num_port] .write(0);
[2]	277
[50]	278	cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl;
[2]	279
[50]	280	TEST(Tdata_t,READ_DATA [num_port].read(), tab[read_address [num_port]]);
	281	nb_ack ++;
	282	}
	283	}
[2]	284
[55]	285	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
	286	{
	287	if ((READ_WRITE_ACK [num_port].read() == 1) and
	288	(READ_WRITE_VAL [num_port].read() == 1))
	289	{
	290	READ_WRITE_VAL [num_port] .write(0);
	291
	292	cout << "(" << num_port << ") [" << read_write_address [num_port] << "] => " << READ_WRITE_RDATA [num_port].read() << endl;
	293
	294	TEST(Tdata_t,READ_WRITE_RDATA [num_port].read(), tab[read_write_address [num_port]]);
	295	nb_ack ++;
	296	}
	297	}
	298
[50]	299	sc_start(0);
[2]	300	}
	301	}
	302
	303	/********************************************************
	304	* Simulation - End
	305	********************************************************/
	306
[50]	307	TEST_STR(bool,true,true, "End of Simulation");
	308	delete _time;
[2]	309	cout << "<" << name << "> ............ Stop Simulation" << endl;
	310
	311	#endif
	312
	313	delete registerfile;
	314	}

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