[2] | 1 | /* |
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| 2 | * $Id: test.cpp 94 2008-12-15 11:04:03Z rosiere $ |
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| 3 | * |
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[94] | 4 | * [ Description ] |
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[2] | 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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[94] | 9 | #define NB_ITERATION 1 |
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| 10 | #define CYCLE_MAX 100000*NB_ITERATION |
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[15] | 11 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h" |
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[44] | 12 | #include "Common/include/Test.h" |
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[2] | 13 | |
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| 14 | void test (string name, |
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[55] | 15 | morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param) |
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[2] | 16 | { |
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| 17 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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| 18 | |
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| 19 | try |
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| 20 | { |
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[55] | 21 | cout << _param->print(1); |
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| 22 | _param->test(); |
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[2] | 23 | } |
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| 24 | catch (morpheo::ErrorMorpheo & error) |
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| 25 | { |
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| 26 | cout << "<" << name << "> : " << error.what (); |
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| 27 | return; |
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| 28 | } |
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| 29 | catch (...) |
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| 30 | { |
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| 31 | cerr << "<" << name << "> : This test must generate a error" << endl; |
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| 32 | exit (EXIT_FAILURE); |
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| 33 | } |
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| 34 | |
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[88] | 35 | Tusage_t _usage = USE_ALL; |
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| 36 | |
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| 37 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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| 38 | // _usage = usage_unset(_usage,USE_VHDL ); |
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| 39 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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| 40 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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| 41 | // _usage = usage_unset(_usage,USE_POSITION ); |
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| 42 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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| 43 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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| 44 | |
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[55] | 45 | #ifdef STATISTICS |
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[71] | 46 | morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,100); |
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[55] | 47 | #endif |
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[82] | 48 | RegisterFile_Monolithic * registerfile = new RegisterFile_Monolithic |
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| 49 | (name.c_str() |
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[2] | 50 | #ifdef STATISTICS |
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[82] | 51 | ,_param_stat |
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[2] | 52 | #endif |
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[82] | 53 | ,_param |
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[88] | 54 | ,_usage); |
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[2] | 55 | |
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| 56 | #ifdef SYSTEMC |
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| 57 | /********************************************************************* |
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| 58 | * Déclarations des signaux |
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| 59 | *********************************************************************/ |
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| 60 | sc_clock CLOCK ("clock", 1.0, 0.5); |
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[6] | 61 | sc_signal<Tcontrol_t> NRESET; |
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[2] | 62 | |
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[55] | 63 | sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read]; |
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| 64 | sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read]; |
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| 65 | sc_signal<Taddress_t> READ_ADDRESS [_param->_nb_port_read]; |
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| 66 | sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read]; |
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[2] | 67 | |
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[55] | 68 | sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write]; |
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| 69 | sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write]; |
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| 70 | sc_signal<Taddress_t> WRITE_ADDRESS [_param->_nb_port_write]; |
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| 71 | sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write]; |
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[2] | 72 | |
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[55] | 73 | sc_signal<Tcontrol_t> READ_WRITE_VAL [_param->_nb_port_read_write]; |
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| 74 | sc_signal<Tcontrol_t> READ_WRITE_ACK [_param->_nb_port_read_write]; |
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| 75 | sc_signal<Tcontrol_t> READ_WRITE_RW [_param->_nb_port_read_write]; |
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| 76 | sc_signal<Taddress_t> READ_WRITE_ADDRESS [_param->_nb_port_read_write]; |
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| 77 | sc_signal<Tdata_t> READ_WRITE_RDATA [_param->_nb_port_read_write]; |
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| 78 | sc_signal<Tdata_t> READ_WRITE_WDATA [_param->_nb_port_read_write]; |
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| 79 | |
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[2] | 80 | /******************************************************** |
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| 81 | * Instanciation |
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| 82 | ********************************************************/ |
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| 83 | |
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[15] | 84 | cout << "<" << name << "> Instanciation of registerfile" << endl; |
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[2] | 85 | |
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| 86 | (*(registerfile->in_CLOCK)) (CLOCK); |
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[6] | 87 | (*(registerfile->in_NRESET)) (NRESET); |
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[2] | 88 | |
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[55] | 89 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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[2] | 90 | { |
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[6] | 91 | (*(registerfile-> in_READ_VAL [i])) (READ_VAL [i]); |
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| 92 | (*(registerfile->out_READ_ACK [i])) (READ_ACK [i]); |
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[62] | 93 | if (_param->_have_port_address) |
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[2] | 94 | (*(registerfile-> in_READ_ADDRESS [i])) (READ_ADDRESS [i]); |
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| 95 | (*(registerfile->out_READ_DATA [i])) (READ_DATA [i]); |
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| 96 | } |
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[55] | 97 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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[2] | 98 | { |
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[6] | 99 | (*(registerfile-> in_WRITE_VAL [i])) (WRITE_VAL [i]); |
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| 100 | (*(registerfile->out_WRITE_ACK [i])) (WRITE_ACK [i]); |
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[62] | 101 | if (_param->_have_port_address) |
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[2] | 102 | (*(registerfile-> in_WRITE_ADDRESS [i])) (WRITE_ADDRESS [i]); |
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| 103 | (*(registerfile-> in_WRITE_DATA [i])) (WRITE_DATA [i]); |
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| 104 | } |
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[55] | 105 | for (uint32_t i=0; i<_param->_nb_port_read_write; i++) |
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| 106 | { |
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| 107 | (*(registerfile-> in_READ_WRITE_VAL [i])) (READ_WRITE_VAL [i]); |
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| 108 | (*(registerfile->out_READ_WRITE_ACK [i])) (READ_WRITE_ACK [i]); |
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| 109 | (*(registerfile-> in_READ_WRITE_RW [i])) (READ_WRITE_RW [i]); |
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[62] | 110 | if (_param->_have_port_address) |
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[55] | 111 | (*(registerfile-> in_READ_WRITE_ADDRESS [i])) (READ_WRITE_ADDRESS [i]); |
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| 112 | (*(registerfile-> in_READ_WRITE_WDATA [i])) (READ_WRITE_WDATA [i]); |
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| 113 | (*(registerfile->out_READ_WRITE_RDATA [i])) (READ_WRITE_RDATA [i]); |
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| 114 | } |
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[2] | 115 | |
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[50] | 116 | cout << "<" << name << "> Start Simulation ............" << endl; |
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| 117 | Time * _time = new Time(); |
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| 118 | |
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[2] | 119 | /******************************************************** |
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| 120 | * Simulation - Begin |
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| 121 | ********************************************************/ |
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| 122 | |
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| 123 | // Initialisation |
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| 124 | |
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| 125 | sc_start(0); |
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| 126 | |
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[55] | 127 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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[6] | 128 | WRITE_VAL [i] .write (0); |
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[55] | 129 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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[6] | 130 | READ_VAL [i] .write (0); |
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[55] | 131 | for (uint32_t i=0; i<_param->_nb_port_read_write; i++) |
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| 132 | READ_WRITE_VAL [i] .write (0); |
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[2] | 133 | |
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[42] | 134 | NRESET.write(0); |
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| 135 | |
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[2] | 136 | sc_start(5); |
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| 137 | |
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[42] | 138 | NRESET.write(1); |
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| 139 | |
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[2] | 140 | |
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[50] | 141 | for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++) |
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| 142 | { |
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| 143 | cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl; |
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[2] | 144 | |
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[50] | 145 | // random init |
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| 146 | uint32_t grain = 0; |
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| 147 | //uint32_t grain = static_cast<uint32_t>(time(NULL)); |
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[2] | 148 | |
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[50] | 149 | srand(grain); |
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[2] | 150 | |
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[55] | 151 | Tdata_t tab [_param->_nb_word]; |
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[50] | 152 | |
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[55] | 153 | for (uint32_t i=0; i<_param->_nb_word; i++) |
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| 154 | tab[i]= rand()%(1<<(_param->_size_word-1)); |
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[50] | 155 | |
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| 156 | Taddress_t address_next = 0; |
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| 157 | Taddress_t nb_ack = 0; |
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| 158 | |
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[55] | 159 | while (nb_ack < _param->_nb_word) |
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[2] | 160 | { |
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[50] | 161 | cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; |
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[2] | 162 | |
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[55] | 163 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
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[50] | 164 | { |
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[55] | 165 | if ((address_next < _param->_nb_word) and |
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[50] | 166 | (WRITE_VAL [num_port].read() == 0)) |
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| 167 | { |
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| 168 | cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl; |
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| 169 | |
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| 170 | WRITE_VAL [num_port] .write(1); |
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| 171 | WRITE_DATA [num_port] .write(tab[address_next]); |
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| 172 | WRITE_ADDRESS [num_port] .write(address_next++); |
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| 173 | |
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| 174 | // Address can be not a multiple of nb_port_write |
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[55] | 175 | if (address_next >= _param->_nb_word) |
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[50] | 176 | break; |
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| 177 | } |
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| 178 | } |
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[55] | 179 | |
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| 180 | for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) |
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| 181 | { |
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| 182 | if ((address_next < _param->_nb_word) and |
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| 183 | (READ_WRITE_VAL [num_port].read() == 0)) |
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| 184 | { |
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| 185 | cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl; |
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| 186 | |
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| 187 | READ_WRITE_VAL [num_port] .write(1); |
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| 188 | READ_WRITE_RW [num_port] .write(RW_WRITE); |
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| 189 | READ_WRITE_WDATA [num_port] .write(tab[address_next]); |
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| 190 | READ_WRITE_ADDRESS [num_port] .write(address_next++); |
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| 191 | |
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| 192 | // Address can be not a multiple of nb_port_write |
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| 193 | if (address_next >= _param->_nb_word) |
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| 194 | break; |
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| 195 | } |
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| 196 | } |
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[50] | 197 | |
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| 198 | sc_start(1); |
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[2] | 199 | |
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[50] | 200 | // reset write_val port |
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[55] | 201 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
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[50] | 202 | { |
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| 203 | if ((WRITE_ACK [num_port].read() == 1) and |
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| 204 | (WRITE_VAL [num_port].read() == 1)) |
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| 205 | { |
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| 206 | WRITE_VAL [num_port] .write(0); |
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| 207 | nb_ack ++; |
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| 208 | } |
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| 209 | } |
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[55] | 210 | // reset write_val port |
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| 211 | for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) |
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| 212 | { |
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| 213 | if ((READ_WRITE_ACK [num_port].read() == 1) and |
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| 214 | (READ_WRITE_VAL [num_port].read() == 1)) |
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| 215 | { |
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| 216 | READ_WRITE_VAL [num_port] .write(0); |
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| 217 | nb_ack ++; |
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| 218 | } |
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| 219 | } |
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[2] | 220 | |
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[50] | 221 | sc_start(0); |
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[2] | 222 | } |
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[50] | 223 | |
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| 224 | address_next = 0; |
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| 225 | nb_ack = 0; |
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[2] | 226 | |
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[50] | 227 | cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl; |
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| 228 | |
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[55] | 229 | Tdata_t read_address [_param->_nb_port_read]; |
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| 230 | Tdata_t read_write_address [_param->_nb_port_read_write]; |
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[2] | 231 | |
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[55] | 232 | while (nb_ack < _param->_nb_word) |
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[50] | 233 | { |
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| 234 | cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; |
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| 235 | |
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[55] | 236 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
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[50] | 237 | { |
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[55] | 238 | if ((address_next < _param->_nb_word) and |
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[50] | 239 | (READ_VAL [num_port].read() == 0)) |
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| 240 | { |
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| 241 | read_address [num_port] = address_next++; |
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[2] | 242 | |
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[50] | 243 | READ_VAL [num_port].write(1); |
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| 244 | READ_ADDRESS [num_port].write(read_address [num_port]); |
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[2] | 245 | |
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[55] | 246 | if (address_next >= _param->_nb_word) |
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[50] | 247 | break; |
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| 248 | } |
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| 249 | } |
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[2] | 250 | |
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[55] | 251 | for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) |
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| 252 | { |
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| 253 | if ((address_next < _param->_nb_word) and |
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| 254 | (READ_WRITE_VAL [num_port].read() == 0)) |
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| 255 | { |
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| 256 | read_write_address [num_port] = address_next++; |
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| 257 | |
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| 258 | READ_WRITE_VAL [num_port].write(1); |
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| 259 | READ_WRITE_RW [num_port].write(RW_READ); |
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| 260 | READ_WRITE_ADDRESS [num_port].write(read_write_address [num_port]); |
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| 261 | |
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| 262 | if (address_next >= _param->_nb_word) |
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| 263 | break; |
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| 264 | } |
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| 265 | } |
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| 266 | |
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| 267 | |
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[50] | 268 | sc_start(1); |
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[2] | 269 | |
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[50] | 270 | // reset write_val port |
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[55] | 271 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
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[50] | 272 | { |
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| 273 | if ((READ_ACK [num_port].read() == 1) and |
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| 274 | (READ_VAL [num_port].read() == 1)) |
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| 275 | { |
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| 276 | READ_VAL [num_port] .write(0); |
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[2] | 277 | |
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[50] | 278 | cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl; |
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[2] | 279 | |
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[50] | 280 | TEST(Tdata_t,READ_DATA [num_port].read(), tab[read_address [num_port]]); |
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| 281 | nb_ack ++; |
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| 282 | } |
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| 283 | } |
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[2] | 284 | |
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[55] | 285 | for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) |
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| 286 | { |
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| 287 | if ((READ_WRITE_ACK [num_port].read() == 1) and |
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| 288 | (READ_WRITE_VAL [num_port].read() == 1)) |
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| 289 | { |
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| 290 | READ_WRITE_VAL [num_port] .write(0); |
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| 291 | |
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| 292 | cout << "(" << num_port << ") [" << read_write_address [num_port] << "] => " << READ_WRITE_RDATA [num_port].read() << endl; |
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| 293 | |
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| 294 | TEST(Tdata_t,READ_WRITE_RDATA [num_port].read(), tab[read_write_address [num_port]]); |
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| 295 | nb_ack ++; |
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| 296 | } |
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| 297 | } |
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| 298 | |
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[50] | 299 | sc_start(0); |
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[2] | 300 | } |
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| 301 | } |
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| 302 | |
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| 303 | /******************************************************** |
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| 304 | * Simulation - End |
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| 305 | ********************************************************/ |
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| 306 | |
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[50] | 307 | TEST_STR(bool,true,true, "End of Simulation"); |
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| 308 | delete _time; |
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[2] | 309 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
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| 310 | |
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| 311 | #endif |
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| 312 | |
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| 313 | delete registerfile; |
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| 314 | } |
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