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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp @ 109

Last change on this file since 109 was 109, checked in by rosiere, 15 years ago
1) Configuration : instance configuration file : regroup similar instance 2) Configuration : timing default = 0 3) Debug/Commit_unit : Add watch dog timer 4) Issue_queue : Test parameters : add test if type is optionnal 5) Cor_glue : Fix insert index 6) Free_list : remove bank_by_pop (else deadlock) 7) Update Free List : add register to source event
Property svn:keywords set to `Id`
File size: 5.1 KB

Rev	Line
[2]	1	/*
	2	* $Id: RegisterFile_Monolithic_allocation.cpp 109 2009-02-16 20:28:31Z rosiere $
	3	*
[109]	4	* [ Description ]
[2]	5	*
	6	*/
	7
[15]	8	#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h"
[2]	9
	10	namespace morpheo {
	11	namespace behavioural {
	12	namespace generic {
	13	namespace registerfile {
[15]	14	namespace registerfile_monolithic {
[2]	15
[15]	16	void RegisterFile_Monolithic::allocation (void)
[2]	17	{
[57]	18	_component = new Component (_usage);
[42]	19
	20	Entity * entity = _component->set_entity (_name
	21	,"RegisterFile_Monolithic"
[41]	22	#ifdef POSITION
[42]	23	,REGISTER
	24	#endif
	25	);
[41]	26
	27	_interfaces = entity->set_interfaces();
	28
[109]	29	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[42]	30	{
	31	Interface * interface = _interfaces->set_interface(""
	32	#ifdef POSITION
	33	, IN
	34	,SOUTH
	35	, "Generalist interface"
	36	#endif
	37	);
	38
	39	in_CLOCK = interface->set_signal_clk ("clock" ,1);
	40	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
	41	}
[109]	42	// ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[41]	43
[55]	44	in_READ_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read];
	45	out_READ_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read];
[62]	46	if (_param->_have_port_address)
[55]	47	in_READ_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read];
	48	out_READ_DATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read];
[2]	49
[55]	50	for (uint32_t i=0; i<_param->_nb_port_read; i++)
[41]	51	{
[42]	52	Interface_fifo * interface = _interfaces->set_interface("read_"+toString(i)
	53	#ifdef POSITION
	54	, IN
	55	,WEST
	56	, "Interface Read"
	57	#endif
	58	);
[2]	59
[42]	60	in_READ_VAL [i] = interface->set_signal_valack_in ("val" , VAL);
	61	out_READ_ACK [i] = interface->set_signal_valack_out ("ack" , ACK);
[62]	62	if (_param->_have_port_address)
[55]	63	in_READ_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", _param->_size_address);
	64	out_READ_DATA [i] = interface->set_signal_out <Tdata_t > ("data" , _param->_size_word);
[41]	65	}
[2]	66
[109]	67	// ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[6]	68
[55]	69	in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_write];
	70	out_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_write];
[62]	71	if (_param->_have_port_address)
[55]	72	in_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_write];
	73	in_WRITE_DATA = new SC_IN (Tdata_t ) * [_param->_nb_port_write];
[2]	74
[55]	75	for (uint32_t i=0; i<_param->_nb_port_write; i++)
[2]	76	{
[42]	77	Interface_fifo * interface = _interfaces->set_interface("write_"+toString(i)
	78	#ifdef POSITION
	79	, IN
	80	,EAST
	81	, "Interface Write"
	82	#endif
	83	);
[2]	84
[42]	85	in_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL);
	86	out_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK);
[62]	87	if (_param->_have_port_address)
[55]	88	in_WRITE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", _param->_size_address);
	89	in_WRITE_DATA [i] = interface->set_signal_in <Tdata_t > ("data" , _param->_size_word);
[2]	90	}
	91
[109]	92	// ~~~~~[ Interface : "read_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[55]	93
	94	in_READ_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read_write];
	95	out_READ_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read_write];
	96	in_READ_WRITE_RW = new SC_IN (Tcontrol_t) * [_param->_nb_port_read_write];
[62]	97	if (_param->_have_port_address)
[55]	98	in_READ_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read_write];
	99	in_READ_WRITE_WDATA = new SC_IN (Tdata_t ) * [_param->_nb_port_read_write];
	100	out_READ_WRITE_RDATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read_write];
	101
	102	for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
	103	{
	104	Interface_fifo * interface = _interfaces->set_interface("read_write_"+toString(i)
	105	#ifdef POSITION
	106	, IN
	107	,WEST
	108	, "Interface Read_Write"
	109	#endif
	110	);
	111
	112	in_READ_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL);
	113	out_READ_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK);
	114	in_READ_WRITE_RW [i] = interface->set_signal_valack_in ("rw" , VAL);
[62]	115	if (_param->_have_port_address)
[55]	116	in_READ_WRITE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", _param->_size_address);
	117	in_READ_WRITE_WDATA [i] = interface->set_signal_in <Tdata_t > ("wdata" , _param->_size_word);
	118	out_READ_WRITE_RDATA [i] = interface->set_signal_out <Tdata_t > ("rdata" , _param->_size_word);
	119	}
	120
[2]	121	// ----- Register
[88]	122	if (usage_is_set(_usage,USE_SYSTEMC))
	123	reg_DATA = new Tdata_t [_param->_nb_word];
[2]	124
[41]	125	#ifdef POSITION
[88]	126	if (usage_is_set(_usage,USE_POSITION))
	127	_component->generate_file();
[41]	128	#endif
[2]	129	};
	130
[15]	131	}; // end namespace registerfile_monolithic
[2]	132	}; // end namespace registerfile
	133	}; // end namespace generic
	134	}; // end namespace behavioural
	135	}; // end namespace morpheo

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