source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp @ 112

Last change on this file since 112 was 112, checked in by rosiere, 15 years ago

1) Stat_list : fix retire old and new register bug
2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step)
3) Model : add class Model (cf Morpheo.sim)
4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array.
5) Script : add distexe.sh
6) Add Comparator, Multiplier, Divider. But this component are not implemented
7) Software : add Dhrystone
  • Property svn:keywords set to Id
File size: 3.2 KB
RevLine 
[2]1/*
2 * $Id: RegisterFile_Monolithic_allocation.cpp 112 2009-03-18 22:36:26Z rosiere $
3 *
[109]4 * [ Description ]
[2]5 *
6 */
7
[15]8#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h"
[112]9#include "Behavioural/include/Allocation.h"
[2]10
11namespace morpheo                    {
12namespace behavioural                {
13namespace generic                    {
14namespace registerfile               {
[15]15namespace registerfile_monolithic    {
[2]16
[15]17  void RegisterFile_Monolithic::allocation (void)
[2]18  {
[57]19    _component   = new Component (_usage);
[42]20
21    Entity * entity = _component->set_entity (_name                   
22                                             ,"RegisterFile_Monolithic"
[41]23#ifdef POSITION
[42]24                                             ,REGISTER                 
25#endif
26                                              );
[41]27   
28    _interfaces = entity->set_interfaces();
29
[109]30    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[42]31    {
32      Interface * interface = _interfaces->set_interface(""
33#ifdef POSITION
34                                                         , IN
35                                                         ,SOUTH
[112]36                                                         ,_("Generalist interface")
[42]37#endif
38                                                         );
39     
40      in_CLOCK              = interface->set_signal_clk              ("clock" ,1);
41      in_NRESET             = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
42    }
[112]43
[109]44    // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[112]45    { 
46      ALLOC1_INTERFACE_BEGIN("read",IN,WEST,_("Interface Read"),_param->_nb_port_read);
[41]47
[112]48      ALLOC1_VALACK_IN ( in_READ_VAL    ,VAL);
49      ALLOC1_VALACK_OUT(out_READ_ACK    ,ACK);
50      ALLOC1_SIGNAL_IN ( in_READ_ADDRESS,"address",Taddress_t,_param->_size_address);
51      ALLOC1_SIGNAL_OUT(out_READ_DATA   ,"data"   ,Tdata_t   ,_param->_size_word);
[2]52
[112]53      ALLOC1_INTERFACE_END(_param->_nb_port_read);
54    }
[2]55
[109]56    // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[112]57    {
58      ALLOC1_INTERFACE_BEGIN("write",IN,EAST,_("Interface Write"),_param->_nb_port_write);
[6]59
[112]60      ALLOC1_VALACK_IN ( in_WRITE_VAL    ,VAL);
61      ALLOC1_VALACK_OUT(out_WRITE_ACK    ,ACK);
62      ALLOC1_SIGNAL_IN ( in_WRITE_ADDRESS,"address",Taddress_t,_param->_size_address);
63      ALLOC1_SIGNAL_IN ( in_WRITE_DATA   ,"data"   ,Tdata_t   ,_param->_size_word);
[2]64
[112]65      ALLOC1_INTERFACE_END(_param->_nb_port_write);
66    }
[2]67
[109]68    // ~~~~~[ Interface : "read_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[112]69    { 
70      ALLOC1_INTERFACE_BEGIN("read_write",IN,WEST,_("Interface Read_Write"),_param->_nb_port_read_write);
[55]71
[112]72      ALLOC1_VALACK_IN ( in_READ_WRITE_VAL    ,VAL);
73      ALLOC1_VALACK_OUT(out_READ_WRITE_ACK    ,ACK);
74      ALLOC1_SIGNAL_IN ( in_READ_WRITE_RW     ,"rw"     ,Tcontrol_t,1);
75      ALLOC1_SIGNAL_IN ( in_READ_WRITE_ADDRESS,"address",Taddress_t,_param->_size_address);
76      ALLOC1_SIGNAL_IN ( in_READ_WRITE_WDATA  ,"wdata"  ,Tdata_t   ,_param->_size_word);
77      ALLOC1_SIGNAL_OUT(out_READ_WRITE_RDATA  ,"rdata"  ,Tdata_t   ,_param->_size_word);
[55]78
[112]79      ALLOC1_INTERFACE_END(_param->_nb_port_read_write);
80    }
[55]81
[88]82    if (usage_is_set(_usage,USE_SYSTEMC))
[112]83      ALLOC1(reg_DATA,Tdata_t,_param->_nb_word);
[2]84   
[41]85#ifdef POSITION
[88]86    if (usage_is_set(_usage,USE_POSITION))
87      _component->generate_file();
[41]88#endif
[2]89  };
90
[15]91}; // end namespace registerfile_monolithic
[2]92}; // end namespace registerfile
93}; // end namespace generic
94}; // end namespace behavioural         
95}; // end namespace morpheo             
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