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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_allocation.cpp @ 59

Last change on this file since 59 was 57, checked in by rosiere, 17 years ago
VHDL - RegisterFile_Multi_Banked (only partial_crossbar) SystemC - modif Component, interface and co -> ajout du type Tusage_T pour instancier un coposant mais ne demander que le VHDL ou le systemC. Séminaire interne
File size: 5.0 KB

Rev	Line
[2]	1	/*
	2	* $Id$
	3	*
	4	* [ Description ]
	5	*
	6	*/
	7
[15]	8	#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h"
[2]	9
	10	namespace morpheo {
	11	namespace behavioural {
	12	namespace generic {
	13	namespace registerfile {
[15]	14	namespace registerfile_monolithic {
[2]	15
[15]	16	void RegisterFile_Monolithic::allocation (void)
[2]	17	{
[57]	18	_component = new Component (_usage);
[42]	19
	20	Entity * entity = _component->set_entity (_name
	21	,"RegisterFile_Monolithic"
[41]	22	#ifdef POSITION
[42]	23	,REGISTER
	24	#endif
	25	);
[41]	26
	27	_interfaces = entity->set_interfaces();
	28
	29	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[42]	30	{
	31	Interface * interface = _interfaces->set_interface(""
	32	#ifdef POSITION
	33	, IN
	34	,SOUTH
	35	, "Generalist interface"
	36	#endif
	37	);
	38
	39	in_CLOCK = interface->set_signal_clk ("clock" ,1);
	40	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
	41	}
[41]	42	// ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	43
[55]	44	in_READ_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read];
	45	out_READ_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read];
	46	in_READ_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read];
	47	out_READ_DATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read];
[2]	48
[55]	49	for (uint32_t i=0; i<_param->_nb_port_read; i++)
[41]	50	{
[42]	51	Interface_fifo * interface = _interfaces->set_interface("read_"+toString(i)
	52	#ifdef POSITION
	53	, IN
	54	,WEST
	55	, "Interface Read"
	56	#endif
	57	);
[2]	58
[42]	59	in_READ_VAL [i] = interface->set_signal_valack_in ("val" , VAL);
	60	out_READ_ACK [i] = interface->set_signal_valack_out ("ack" , ACK);
[55]	61	in_READ_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", _param->_size_address);
	62	out_READ_DATA [i] = interface->set_signal_out <Tdata_t > ("data" , _param->_size_word);
[41]	63	}
[2]	64
[41]	65	// ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[6]	66
[55]	67	in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_write];
	68	out_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_write];
	69	in_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_write];
	70	in_WRITE_DATA = new SC_IN (Tdata_t ) * [_param->_nb_port_write];
[2]	71
[55]	72	for (uint32_t i=0; i<_param->_nb_port_write; i++)
[2]	73	{
[42]	74	Interface_fifo * interface = _interfaces->set_interface("write_"+toString(i)
	75	#ifdef POSITION
	76	, IN
	77	,EAST
	78	, "Interface Write"
	79	#endif
	80	);
[2]	81
[42]	82	in_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL);
	83	out_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK);
[55]	84	in_WRITE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", _param->_size_address);
	85	in_WRITE_DATA [i] = interface->set_signal_in <Tdata_t > ("data" , _param->_size_word);
[2]	86	}
	87
[55]	88	// ~~~~~[ Interface : "read_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	89
	90	in_READ_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read_write];
	91	out_READ_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read_write];
	92	in_READ_WRITE_RW = new SC_IN (Tcontrol_t) * [_param->_nb_port_read_write];
	93	in_READ_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read_write];
	94	in_READ_WRITE_WDATA = new SC_IN (Tdata_t ) * [_param->_nb_port_read_write];
	95	out_READ_WRITE_RDATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read_write];
	96
	97	for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
	98	{
	99	Interface_fifo * interface = _interfaces->set_interface("read_write_"+toString(i)
	100	#ifdef POSITION
	101	, IN
	102	,WEST
	103	, "Interface Read_Write"
	104	#endif
	105	);
	106
	107	in_READ_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL);
	108	out_READ_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK);
	109	in_READ_WRITE_RW [i] = interface->set_signal_valack_in ("rw" , VAL);
	110	in_READ_WRITE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", _param->_size_address);
	111	in_READ_WRITE_WDATA [i] = interface->set_signal_in <Tdata_t > ("wdata" , _param->_size_word);
	112	out_READ_WRITE_RDATA [i] = interface->set_signal_out <Tdata_t > ("rdata" , _param->_size_word);
	113	}
	114
[2]	115	// ----- Register
[55]	116	reg_DATA = new SC_REGISTER (Tdata_t) * [_param->_nb_word];
[2]	117
[55]	118	for (uint32_t i=0; i<_param->_nb_word; i++)
[2]	119	{
	120	string rename = "reg_DATA[" + toString(i) + "]";
	121	reg_DATA [i] = new SC_REGISTER (Tdata_t) (rename.c_str());
[41]	122	}
	123
	124	#ifdef POSITION
[42]	125	_component->generate_file();
[41]	126	#endif
[2]	127	};
	128
[15]	129	}; // end namespace registerfile_monolithic
[2]	130	}; // end namespace registerfile
	131	}; // end namespace generic
	132	}; // end namespace behavioural
	133	}; // end namespace morpheo

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