1 | /* |
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2 | * $Id$ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | */ |
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7 | |
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8 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h" |
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9 | |
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10 | namespace morpheo { |
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11 | namespace behavioural { |
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12 | namespace generic { |
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13 | namespace registerfile { |
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14 | namespace registerfile_monolithic { |
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15 | |
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16 | void RegisterFile_Monolithic::allocation (void) |
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17 | { |
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18 | _component = new Component (_usage); |
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19 | |
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20 | Entity * entity = _component->set_entity (_name |
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21 | ,"RegisterFile_Monolithic" |
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22 | #ifdef POSITION |
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23 | ,REGISTER |
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24 | #endif |
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25 | ); |
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26 | |
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27 | _interfaces = entity->set_interfaces(); |
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28 | |
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29 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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30 | { |
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31 | Interface * interface = _interfaces->set_interface("" |
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32 | #ifdef POSITION |
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33 | , IN |
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34 | ,SOUTH |
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35 | , "Generalist interface" |
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36 | #endif |
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37 | ); |
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38 | |
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39 | in_CLOCK = interface->set_signal_clk ("clock" ,1); |
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40 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); |
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41 | } |
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42 | // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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43 | |
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44 | in_READ_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read]; |
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45 | out_READ_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read]; |
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46 | if (_param->_have_port_address) |
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47 | in_READ_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read]; |
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48 | out_READ_DATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read]; |
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49 | |
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50 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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51 | { |
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52 | Interface_fifo * interface = _interfaces->set_interface("read_"+toString(i) |
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53 | #ifdef POSITION |
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54 | , IN |
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55 | ,WEST |
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56 | , "Interface Read" |
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57 | #endif |
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58 | ); |
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59 | |
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60 | in_READ_VAL [i] = interface->set_signal_valack_in ("val" , VAL); |
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61 | out_READ_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); |
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62 | if (_param->_have_port_address) |
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63 | in_READ_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", _param->_size_address); |
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64 | out_READ_DATA [i] = interface->set_signal_out <Tdata_t > ("data" , _param->_size_word); |
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65 | } |
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66 | |
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67 | // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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68 | |
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69 | in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_write]; |
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70 | out_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_write]; |
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71 | if (_param->_have_port_address) |
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72 | in_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_write]; |
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73 | in_WRITE_DATA = new SC_IN (Tdata_t ) * [_param->_nb_port_write]; |
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74 | |
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75 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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76 | { |
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77 | Interface_fifo * interface = _interfaces->set_interface("write_"+toString(i) |
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78 | #ifdef POSITION |
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79 | , IN |
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80 | ,EAST |
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81 | , "Interface Write" |
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82 | #endif |
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83 | ); |
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84 | |
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85 | in_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); |
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86 | out_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); |
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87 | if (_param->_have_port_address) |
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88 | in_WRITE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", _param->_size_address); |
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89 | in_WRITE_DATA [i] = interface->set_signal_in <Tdata_t > ("data" , _param->_size_word); |
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90 | } |
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91 | |
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92 | // ~~~~~[ Interface : "read_write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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93 | |
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94 | in_READ_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read_write]; |
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95 | out_READ_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read_write]; |
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96 | in_READ_WRITE_RW = new SC_IN (Tcontrol_t) * [_param->_nb_port_read_write]; |
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97 | if (_param->_have_port_address) |
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98 | in_READ_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read_write]; |
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99 | in_READ_WRITE_WDATA = new SC_IN (Tdata_t ) * [_param->_nb_port_read_write]; |
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100 | out_READ_WRITE_RDATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read_write]; |
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101 | |
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102 | for (uint32_t i=0; i<_param->_nb_port_read_write; i++) |
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103 | { |
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104 | Interface_fifo * interface = _interfaces->set_interface("read_write_"+toString(i) |
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105 | #ifdef POSITION |
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106 | , IN |
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107 | ,WEST |
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108 | , "Interface Read_Write" |
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109 | #endif |
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110 | ); |
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111 | |
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112 | in_READ_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); |
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113 | out_READ_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); |
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114 | in_READ_WRITE_RW [i] = interface->set_signal_valack_in ("rw" , VAL); |
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115 | if (_param->_have_port_address) |
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116 | in_READ_WRITE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", _param->_size_address); |
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117 | in_READ_WRITE_WDATA [i] = interface->set_signal_in <Tdata_t > ("wdata" , _param->_size_word); |
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118 | out_READ_WRITE_RDATA [i] = interface->set_signal_out <Tdata_t > ("rdata" , _param->_size_word); |
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119 | } |
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120 | |
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121 | // ----- Register |
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122 | reg_DATA = new SC_REGISTER (Tdata_t) * [_param->_nb_word]; |
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123 | |
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124 | for (uint32_t i=0; i<_param->_nb_word; i++) |
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125 | { |
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126 | string rename = "reg_DATA[" + toString(i) + "]"; |
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127 | reg_DATA [i] = new SC_REGISTER (Tdata_t) (rename.c_str()); |
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128 | } |
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129 | |
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130 | #ifdef POSITION |
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131 | _component->generate_file(); |
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132 | #endif |
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133 | }; |
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134 | |
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135 | }; // end namespace registerfile_monolithic |
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136 | }; // end namespace registerfile |
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137 | }; // end namespace generic |
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138 | }; // end namespace behavioural |
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139 | }; // end namespace morpheo |
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