source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp @ 62

Last change on this file since 62 was 62, checked in by rosiere, 17 years ago

Modification en profondeur de Component-port_map.
Compilation ok pour Register_unit ... a tester (systemC et vhdl)

File size: 2.2 KB
Line 
1#ifdef SYSTEMC
2/*
3 * $Id$
4 *
5 * [ Description ]
6 *
7 */
8
9#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h"
10
11namespace morpheo                    {
12namespace behavioural                {
13namespace generic                    {
14namespace registerfile               {
15namespace registerfile_monolithic    {
16  void RegisterFile_Monolithic::transition (void)
17  {
18    log_printf(FUNC,RegisterFile,"transition","Begin");
19#ifdef STATISTICS
20    _stat_nb_write = 0;
21#endif   
22
23    for (uint32_t i=0; i<_param->_nb_port_write; i++)
24      {
25        // Have a write?
26        if ( PORT_READ(in_WRITE_VAL[i]) == true)
27          {
28#ifdef STATISTICS
29            _stat_nb_write ++;
30#endif   
31
32            Taddress_t address;
33            if (_param->_have_port_address)
34              address = PORT_READ(in_WRITE_ADDRESS[i]);
35            else
36              address = 0;
37
38            Tdata_t    data    = PORT_READ(in_WRITE_DATA   [i]);
39           
40            log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data));
41
42            // Write in registerFile
43            REGISTER_WRITE(reg_DATA[address],data);
44          }
45      }
46    for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
47      {
48        // Have a read_write?
49        if ( (PORT_READ(in_READ_WRITE_VAL[i]) == true) and
50             (PORT_READ(in_READ_WRITE_RW [i]) == RW_WRITE))
51          {
52#ifdef STATISTICS
53            _stat_nb_write ++;
54#endif   
55
56            Taddress_t address;
57            if (_param->_have_port_address)
58              address = PORT_READ(in_READ_WRITE_ADDRESS[i]);
59            else
60              address = 0;
61            Tdata_t    data    = PORT_READ(in_READ_WRITE_WDATA  [i]);
62           
63            log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data));
64
65            // Write in registerFile
66            REGISTER_WRITE(reg_DATA[address],data);
67          }
68      }
69
70#ifdef STATISTICS
71    _stat->add(_stat_nb_read,_stat_nb_write);
72#endif   
73
74#ifdef VHDL_TESTBENCH
75    vhdl_testbench_transition ();
76#endif
77    log_printf(FUNC,RegisterFile,"transition","End");
78  };
79
80}; // end namespace registerfile_monolithic
81}; // end namespace registerfile
82}; // end namespace generic
83}; // end namespace behavioural         
84}; // end namespace morpheo             
85#endif
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