source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp @ 78

Last change on this file since 78 was 78, checked in by rosiere, 16 years ago

Add :

  • Execute_loop (must be test systemC)
  • Prediction
    • Direction : predifined scheme
    • Branch Target Buffer
  • iFetch_unit
    • ifetch_queue
    • pc management
  • Decod_unit
    • coming soon : support for custom operation
  • Rename_unit
    • RAT
    • Free_list
    • Dependence RAW check
    • Load store unit pointer
  • New Environnement (hierarchy_memory will remove in a next version)


Modif :

  • Manage Custom Operation
  • All component in execute_loop to use the new statistics management

Not Finish :

  • Return Address Stack
  • Environnement
File size: 2.2 KB
Line 
1#ifdef SYSTEMC
2/*
3 * $Id$
4 *
5 * [ Description ]
6 *
7 */
8
9#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/include/RegisterFile_Monolithic.h"
10
11namespace morpheo                    {
12namespace behavioural                {
13namespace generic                    {
14namespace registerfile               {
15namespace registerfile_monolithic    {
16  void RegisterFile_Monolithic::transition (void)
17  {
18    log_printf(FUNC,RegisterFile,"transition","Begin");
19
20    for (uint32_t i=0; i<_param->_nb_port_write; i++)
21      {
22        // Have a write?
23        if ( PORT_READ(in_WRITE_VAL[i]) == true)
24          {
25#ifdef STATISTICS
26            (*_stat_nb_write) ++;
27#endif   
28
29            Taddress_t address;
30            if (_param->_have_port_address)
31              address = PORT_READ(in_WRITE_ADDRESS[i]);
32            else
33              address = 0;
34
35            Tdata_t    data    = PORT_READ(in_WRITE_DATA   [i]);
36           
37            log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data));
38
39            // Write in registerFile
40            reg_DATA[address] = data;
41          }
42      }
43    for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
44      {
45        // Have a read_write?
46        if (PORT_READ(in_READ_WRITE_VAL[i]) == true)
47          {
48            if (PORT_READ(in_READ_WRITE_RW [i]) == RW_WRITE)
49              {
50#ifdef STATISTICS
51                (*_stat_nb_write) ++;
52#endif   
53               
54                Taddress_t address;
55                if (_param->_have_port_address)
56                  address = PORT_READ(in_READ_WRITE_ADDRESS[i]);
57                else
58                  address = 0;
59                Tdata_t    data    = PORT_READ(in_READ_WRITE_WDATA  [i]);
60               
61                log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data));
62               
63                // Write in registerFile
64                reg_DATA[address] = data;
65              }
66#ifdef STATISTICS
67            else
68              {
69                (*_stat_nb_read) ++;
70              }
71#endif   
72          }
73      }
74
75#ifdef STATISTICS
76    for (uint32_t i=0; i<_param->_nb_port_read; i++)
77      if ( PORT_READ(in_READ_VAL [i]) == 1)
78        (*_stat_nb_read) ++;
79#endif   
80
81#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
82    end_cycle();
83#endif
84    log_printf(FUNC,RegisterFile,"transition","End");
85  };
86
87}; // end namespace registerfile_monolithic
88}; // end namespace registerfile
89}; // end namespace generic
90}; // end namespace behavioural         
91}; // end namespace morpheo             
92#endif
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