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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src/test.cpp @ 19

Last change on this file since 19 was 15, checked in by rosiere, 17 years ago
Interface normalisé Début du banc de registres multi niveaux
File size: 19.1 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 16
10
11	#define LABEL(str) do {cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; _RegisterFile_Multi_Banked_Glue->vhdl_testbench_label(str);} while (0)
12
13	#include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/include/test.h"
14	#include "Include/Test.h"
15	#include "Include/BitManipulation.h"
16
17	void test (string name,
18	morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::Parameters _param)
19	{
20	cout << "<" << name << "> : Simulation SystemC" << endl;
21
22	RegisterFile_Multi_Banked_Glue * _RegisterFile_Multi_Banked_Glue = new RegisterFile_Multi_Banked_Glue (name.c_str(),
23	#ifdef STATISTICS
24	morpheo::behavioural::Parameters_Statistics(5,50),
25	#endif
26	_param);
27
28	#ifdef SYSTEMC
29	/*********************************************************************
30	* Déclarations des signaux
31	*********************************************************************/
32	sc_clock * CLOCK;
33
34	sc_signal<Tcontrol_t> ** READ_IN_VAL ;
35	sc_signal<Tcontrol_t> ** READ_IN_ACK ;
36	sc_signal<Taddress_t> ** READ_IN_ADDRESS ;
37	sc_signal<Tdata_t > ** READ_IN_DATA ;
38	sc_signal<Tcontrol_t> **** READ_SELECT_VAL ;
39	sc_signal<Tcontrol_t> **** READ_SELECT_ACK ;
40	sc_signal<Tcontrol_t> *** READ_OUT_VAL ;
41	sc_signal<Tcontrol_t> *** READ_OUT_ACK ;
42	sc_signal<Taddress_t> *** READ_OUT_ADDRESS ;
43	sc_signal<Tdata_t > *** READ_OUT_DATA ;
44	sc_signal<Tcontrol_t> ** WRITE_IN_VAL ;
45	sc_signal<Tcontrol_t> ** WRITE_IN_ACK ;
46	sc_signal<Taddress_t> ** WRITE_IN_ADDRESS ;
47	sc_signal<Tdata_t > ** WRITE_IN_DATA ;
48	sc_signal<Tcontrol_t> **** WRITE_SELECT_VAL ;
49	sc_signal<Tcontrol_t> **** WRITE_SELECT_ACK ;
50	sc_signal<Tcontrol_t> *** WRITE_OUT_VAL ;
51	sc_signal<Tcontrol_t> *** WRITE_OUT_ACK ;
52	sc_signal<Taddress_t> *** WRITE_OUT_ADDRESS ;
53	sc_signal<Tdata_t > *** WRITE_OUT_DATA ;
54
55	string rename;
56
57	CLOCK = new sc_clock ("clock", 1.0, 0.5);
58
59	READ_IN_VAL = new sc_signal<Tcontrol_t> * [_param._nb_port_read];
60	READ_IN_ACK = new sc_signal<Tcontrol_t> * [_param._nb_port_read];
61	READ_IN_ADDRESS = new sc_signal<Taddress_t> * [_param._nb_port_read];
62	READ_IN_DATA = new sc_signal<Tdata_t > * [_param._nb_port_read];
63
64	for (uint32_t i=0; i<_param._nb_port_read; i++)
65	{
66	rename = "READ_IN_VAL_"+toString(i)+" ";
67	READ_IN_VAL [i] = new sc_signal<Tcontrol_t> (rename.c_str());
68	rename = "READ_IN_ACK_"+toString(i)+" ";
69	READ_IN_ACK [i] = new sc_signal<Tcontrol_t> (rename.c_str());
70	rename = "READ_IN_ADDRESS_"+toString(i)+" ";
71	READ_IN_ADDRESS [i] = new sc_signal<Taddress_t> (rename.c_str());
72	rename = "READ_IN_DATA_"+toString(i)+" ";
73	READ_IN_DATA [i] = new sc_signal<Tdata_t > (rename.c_str());
74	}
75
76	READ_SELECT_VAL = new sc_signal<Tcontrol_t> *** [_param._nb_bank];
77	READ_SELECT_ACK = new sc_signal<Tcontrol_t> *** [_param._nb_bank];
78
79	for (uint32_t i=0; i<_param._nb_bank; i++)
80	{
81	READ_SELECT_VAL [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_read_by_bank];
82	READ_SELECT_ACK [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_read_by_bank];
83
84	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
85	{
86	READ_SELECT_VAL [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_read_port [j]];
87	READ_SELECT_ACK [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_read_port [j]];
88
89	for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port [j]; k++)
90	{
91	rename="READ_SELECT_VAL_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ";
92	READ_SELECT_VAL [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str());
93
94	rename="READ_SELECT_ACK_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ";
95	READ_SELECT_ACK [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str());
96	}
97	}
98	}
99
100	READ_OUT_VAL = new sc_signal<Tcontrol_t> ** [_param._nb_bank];
101	READ_OUT_ACK = new sc_signal<Tcontrol_t> ** [_param._nb_bank];
102	READ_OUT_ADDRESS = new sc_signal<Taddress_t> ** [_param._nb_bank];
103	READ_OUT_DATA = new sc_signal<Tdata_t > ** [_param._nb_bank];
104
105	for (uint32_t i=0; i<_param._nb_bank; i++)
106	{
107	READ_OUT_VAL [i] = new sc_signal<Tcontrol_t> * [_param._nb_port_read_by_bank];
108	READ_OUT_ACK [i] = new sc_signal<Tcontrol_t> * [_param._nb_port_read_by_bank];
109	READ_OUT_ADDRESS [i] = new sc_signal<Taddress_t> * [_param._nb_port_read_by_bank];
110	READ_OUT_DATA [i] = new sc_signal<Tdata_t > * [_param._nb_port_read_by_bank];
111
112	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
113	{
114	rename="READ_OUT_VAL_"+toString(i)+"_"+toString(j)+" ";
115	READ_OUT_VAL [i][j] = new sc_signal<Tcontrol_t> (rename.c_str());
116	rename="READ_OUT_ACK_"+toString(i)+"_"+toString(j)+" ";
117	READ_OUT_ACK [i][j] = new sc_signal<Tcontrol_t> (rename.c_str());
118	rename="READ_OUT_ADDRESS_"+toString(i)+"_"+toString(j)+" ";
119	READ_OUT_ADDRESS [i][j] = new sc_signal<Taddress_t> (rename.c_str());
120	rename="READ_OUT_DATA_"+toString(i)+"_"+toString(j)+" ";
121	READ_OUT_DATA [i][j] = new sc_signal<Tdata_t > (rename.c_str());
122	}
123	}
124
125	WRITE_IN_VAL = new sc_signal<Tcontrol_t> * [_param._nb_port_write];
126	WRITE_IN_ACK = new sc_signal<Tcontrol_t> * [_param._nb_port_write];
127	WRITE_IN_ADDRESS = new sc_signal<Taddress_t> * [_param._nb_port_write];
128	WRITE_IN_DATA = new sc_signal<Tdata_t > * [_param._nb_port_write];
129	for (uint32_t i=0; i<_param._nb_port_write; i++)
130	{
131	rename = "WRITE_IN_VAL_"+toString(i)+" ";
132	WRITE_IN_VAL [i] = new sc_signal<Tcontrol_t> (rename.c_str());
133	rename = "WRITE_IN_ACK_"+toString(i)+" ";
134	WRITE_IN_ACK [i] = new sc_signal<Tcontrol_t> (rename.c_str());
135	rename = "WRITE_IN_ADDRESS_"+toString(i)+" ";
136	WRITE_IN_ADDRESS [i] = new sc_signal<Taddress_t> (rename.c_str());
137	rename = "WRITE_IN_DATA_"+toString(i)+" ";
138	WRITE_IN_DATA [i] = new sc_signal<Tdata_t > (rename.c_str());
139	}
140
141	WRITE_SELECT_VAL = new sc_signal<Tcontrol_t> *** [_param._nb_bank];
142	WRITE_SELECT_ACK = new sc_signal<Tcontrol_t> *** [_param._nb_bank];
143
144	for (uint32_t i=0; i<_param._nb_bank; i++)
145	{
146	WRITE_SELECT_VAL [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_write_by_bank];
147	WRITE_SELECT_ACK [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_write_by_bank];
148
149	for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
150	{
151	WRITE_SELECT_VAL [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_write_port [j]];
152	WRITE_SELECT_ACK [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_write_port [j]];
153
154	for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port [j]; k++)
155	{
156	rename="WRITE_SELECT_VAL_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ";
157	WRITE_SELECT_VAL [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str());
158
159	rename="WRITE_SELECT_ACK_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ";
160	WRITE_SELECT_ACK [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str());
161	}
162	}
163	}
164
165	WRITE_OUT_VAL = new sc_signal<Tcontrol_t> ** [_param._nb_bank];
166	WRITE_OUT_ACK = new sc_signal<Tcontrol_t> ** [_param._nb_bank];
167	WRITE_OUT_ADDRESS = new sc_signal<Taddress_t> ** [_param._nb_bank];
168	WRITE_OUT_DATA = new sc_signal<Tdata_t > ** [_param._nb_bank];
169
170	for (uint32_t i=0; i<_param._nb_bank; i++)
171	{
172	WRITE_OUT_VAL [i] = new sc_signal<Tcontrol_t> * [_param._nb_port_write_by_bank];
173	WRITE_OUT_ACK [i] = new sc_signal<Tcontrol_t> * [_param._nb_port_write_by_bank];
174	WRITE_OUT_ADDRESS [i] = new sc_signal<Taddress_t> * [_param._nb_port_write_by_bank];
175	WRITE_OUT_DATA [i] = new sc_signal<Tdata_t > * [_param._nb_port_write_by_bank];
176
177	for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
178	{
179	rename = "WRITE_OUT_VAL_"+toString(i)+"_"+toString(j)+" ";
180	WRITE_OUT_VAL [i][j] = new sc_signal<Tcontrol_t> (rename.c_str());
181	rename = "WRITE_OUT_ACK_"+toString(i)+"_"+toString(j)+" ";
182	WRITE_OUT_ACK [i][j] = new sc_signal<Tcontrol_t> (rename.c_str());
183	rename = "WRITE_OUT_ADDRESS_"+toString(i)+"_"+toString(j)+" ";
184	WRITE_OUT_ADDRESS [i][j] = new sc_signal<Taddress_t> (rename.c_str());
185	rename = "WRITE_OUT_DATA_"+toString(i)+"_"+toString(j)+" ";
186	WRITE_OUT_DATA [i][j] = new sc_signal<Tdata_t > (rename.c_str());
187	}
188	}
189
190	/********************************************************
191	* Instanciation
192	********************************************************/
193
194	cout << "<" << name << "> Instanciation of _RegisterFile_Multi_Banked_Glue" << endl;
195
196	((_RegisterFile_Multi_Banked_Glue->in_CLOCK)) ((CLOCK));
197
198	for (uint32_t i=0; i<_param._nb_port_read; i++)
199	{
200	((_RegisterFile_Multi_Banked_Glue-> in_READ_IN_VAL [i])) ((READ_IN_VAL [i]));
201	((_RegisterFile_Multi_Banked_Glue->out_READ_IN_ACK [i])) ((READ_IN_ACK [i]));
202	((_RegisterFile_Multi_Banked_Glue-> in_READ_IN_ADDRESS [i])) ((READ_IN_ADDRESS [i]));
203	((_RegisterFile_Multi_Banked_Glue->out_READ_IN_DATA [i])) ((READ_IN_DATA [i]));
204	}
205
206	for (uint32_t i=0; i<_param._nb_bank; i++)
207	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
208	for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++)
209	{
210	((_RegisterFile_Multi_Banked_Glue->out_READ_SELECT_VAL [i][j][k])) ((READ_SELECT_VAL [i][j][k]));
211	((_RegisterFile_Multi_Banked_Glue-> in_READ_SELECT_ACK [i][j][k])) ((READ_SELECT_ACK [i][j][k]));
212	}
213
214	for (uint32_t i=0; i<_param._nb_bank; i++)
215	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
216	{
217	((_RegisterFile_Multi_Banked_Glue->out_READ_OUT_VAL [i][j])) ((READ_OUT_VAL [i][j]));
218	((_RegisterFile_Multi_Banked_Glue-> in_READ_OUT_ACK [i][j])) ((READ_OUT_ACK [i][j]));
219	((_RegisterFile_Multi_Banked_Glue->out_READ_OUT_ADDRESS [i][j])) ((READ_OUT_ADDRESS [i][j]));
220	((_RegisterFile_Multi_Banked_Glue-> in_READ_OUT_DATA [i][j])) ((READ_OUT_DATA [i][j]));
221	}
222
223	for (uint32_t i=0; i<_param._nb_port_write; i++)
224	{
225	((_RegisterFile_Multi_Banked_Glue-> in_WRITE_IN_VAL [i])) ((WRITE_IN_VAL [i]));
226	((_RegisterFile_Multi_Banked_Glue->out_WRITE_IN_ACK [i])) ((WRITE_IN_ACK [i]));
227	((_RegisterFile_Multi_Banked_Glue-> in_WRITE_IN_ADDRESS [i])) ((WRITE_IN_ADDRESS [i]));
228	((_RegisterFile_Multi_Banked_Glue-> in_WRITE_IN_DATA [i])) ((WRITE_IN_DATA [i]));
229	}
230
231	for (uint32_t i=0; i<_param._nb_bank; i++)
232	for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
233	for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port[j]; k++)
234	{
235	((_RegisterFile_Multi_Banked_Glue->out_WRITE_SELECT_VAL [i][j][k])) ((WRITE_SELECT_VAL [i][j][k]));
236	((_RegisterFile_Multi_Banked_Glue-> in_WRITE_SELECT_ACK [i][j][k])) ((WRITE_SELECT_ACK [i][j][k]));
237	}
238
239	for (uint32_t i=0; i<_param._nb_bank; i++)
240	for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
241	{
242	((_RegisterFile_Multi_Banked_Glue->out_WRITE_OUT_VAL [i][j])) ((WRITE_OUT_VAL [i][j]));
243	((_RegisterFile_Multi_Banked_Glue-> in_WRITE_OUT_ACK [i][j])) ((WRITE_OUT_ACK [i][j]));
244	((_RegisterFile_Multi_Banked_Glue->out_WRITE_OUT_ADDRESS [i][j])) ((WRITE_OUT_ADDRESS [i][j]));
245	((_RegisterFile_Multi_Banked_Glue->out_WRITE_OUT_DATA [i][j])) ((WRITE_OUT_DATA [i][j]));
246	}
247
248
249	cout << "<" << name << "> Start Simulation ............" << endl;
250
251	/********************************************************
252	* Simulation - Begin
253	********************************************************/
254
255	// Initialisation
256
257	const uint32_t seed = 0;
258	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
259
260	srand(seed);
261
262	sc_start(0);
263
264	LABEL("Initialisation");
265
266	uint32_t read_in_num_bank [_param._nb_port_read]; // Number of bank
267	//Tcontrol_t read_in_valid [_param._nb_port_read];
268	Tcontrol_t read_in_ack [_param._nb_port_read]; // to test
269	Tdata_t read_in_data [_param._nb_port_read]; // to test
270	Tcontrol_t read_out_val [_param._nb_bank][_param._nb_port_read_by_bank];
271	Tcontrol_t read_out_ack [_param._nb_bank][_param._nb_port_read_by_bank];
272	Taddress_t read_out_address [_param._nb_bank][_param._nb_port_read_by_bank];
273	Tcontrol_t read_is_busy [_param._nb_port_read];
274	Tcontrol_t read_select_val [_param._nb_bank][_param._nb_port_read ];
275	Tcontrol_t read_select_ack [_param._nb_bank][_param._nb_port_read ];
276
277	LABEL("Loop of Test");
278
279	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
280	{
281	LABEL("Iteration "+toString(iteration));
282
283	LABEL("Test read_in");
284
285	// Write in interface "read_in"
286	for (uint32_t i=0; i<_param._nb_port_read; i++)
287	{
288	read_in_num_bank [i] = rand() % _param._nb_bank;
289	Tcontrol_t read_in_valid = (rand() % 2) != 0;
290
291	Taddress_t address = (read_in_num_bank[i] << _param._shift_address) \| (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & i);
292
293	read_is_busy [i] = (read_in_valid == 0);
294	read_in_ack [i] = 0;
295	read_in_data [i] = 0;
296	READ_IN_VAL [i]->write(read_in_valid);
297	READ_IN_ADDRESS [i]->write(address);
298
299	for (uint32_t j=0; j<_param._nb_bank; j++)
300	read_select_ack [j][i] = 0;
301	}
302
303	for (uint32_t i=0; i<_param._nb_bank; i++)
304	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
305	{
306	read_out_ack [i][j] = (rand() % 2) != 0;
307	READ_OUT_ACK [i][j]->write(read_out_ack [i][j]);
308	READ_OUT_DATA [i][j]->write((j<<1)\|1); // (j<<1)\|1 afin de n'avoir jamais 0
309	}
310
311	// compute the good read_select
312	for (uint32_t i=0; i<_param._nb_bank; i++)
313	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
314	{
315	bool find = false; // have find a port_in to link with this port_out
316	for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++)
317	{
318
319	uint32_t num_port; // number of port
320
321	// compute the good number of port
322	if (_param._crossbar == FULL_CROSSBAR)
323	num_port = k;
324	else
325	num_port = _param._link_port_read [i];
326
327	read_select_val [i][num_port] = read_out_ack [i][j] && not read_is_busy [num_port];
328
329	if ((read_out_ack [i][j] == 0) \|\| find)
330	read_select_ack [i][num_port] = 0; // read_out is busy or already find
331	else
332	{
333	// find a busy port?
334	find = not read_is_busy [num_port];
335	read_is_busy [num_port]\|= find;
336	read_select_ack [i][num_port] = find;
337
338	if (find)
339	{
340	read_in_ack [num_port] = 1;
341	read_in_data [num_port] = ((j<<1)\|1);
342	read_out_val [i][j] = 1;
343	read_out_address [i][j] = (read_in_num_bank[i] << _param._shift_address) \| (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & i);
344	}
345	}
346
347	READ_SELECT_ACK [i][j][k]->write(read_select_ack [i][num_port]);
348	}
349	}
350
351	// next cycle
352	sc_start(1);
353
354	// // lot of test
355	// public : SC_OUT(Tcontrol_t) ** out_READ_IN_ACK ;
356	// public : SC_OUT(Tdata_t ) ** out_READ_IN_DATA ;
357
358	// public : SC_OUT(Tcontrol_t) **** out_READ_SELECT_VAL ;
359
360	// public : SC_OUT(Tcontrol_t) *** out_READ_OUT_VAL ;
361	// public : SC_OUT(Taddress_t) *** out_READ_OUT_ADDRESS ;
362
363	}
364
365	/********************************************************
366	* Simulation - End
367	********************************************************/
368
369	cout << "<" << name << "> ............ Stop Simulation" << endl;
370
371	delete CLOCK;
372
373	for (uint32_t i=0; i<_param._nb_port_read; i++)
374	{
375	delete READ_IN_VAL [i];
376	delete READ_IN_ACK [i];
377	delete READ_IN_ADDRESS [i];
378	delete READ_IN_DATA [i];
379	}
380
381	delete READ_IN_VAL ;
382	delete READ_IN_ACK ;
383	delete READ_IN_ADDRESS;
384	delete READ_IN_DATA ;
385
386	for (uint32_t i=0; i<_param._nb_bank; i++)
387	{
388	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
389	{
390	for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++)
391	{
392	delete READ_SELECT_VAL [i][j][k];
393	delete READ_SELECT_ACK [i][j][k];
394	}
395	delete READ_SELECT_VAL [i][j];
396	delete READ_SELECT_ACK [i][j];
397	}
398	delete READ_SELECT_VAL [i];
399	delete READ_SELECT_ACK [i];
400	}
401	delete READ_SELECT_VAL;
402	delete READ_SELECT_ACK;
403
404	for (uint32_t i=0; i<_param._nb_bank; i++)
405	{
406	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
407	{
408	delete READ_OUT_VAL [i][j];
409	delete READ_OUT_ACK [i][j];
410	delete READ_OUT_ADDRESS [i][j];
411	delete READ_OUT_DATA [i][j];
412	}
413
414	delete READ_OUT_VAL [i];
415	delete READ_OUT_ACK [i];
416	delete READ_OUT_ADDRESS [i];
417	delete READ_OUT_DATA [i];
418	}
419
420	delete READ_OUT_VAL ;
421	delete READ_OUT_ACK ;
422	delete READ_OUT_ADDRESS;
423	delete READ_OUT_DATA ;
424
425	for (uint32_t i=0; i<_param._nb_port_write; i++)
426	{
427	delete WRITE_IN_VAL [i];
428	delete WRITE_IN_ACK [i];
429	delete WRITE_IN_ADDRESS [i];
430	delete WRITE_IN_DATA [i];
431	}
432
433	delete WRITE_IN_VAL ;
434	delete WRITE_IN_ACK ;
435	delete WRITE_IN_ADDRESS;
436	delete WRITE_IN_DATA ;
437
438	for (uint32_t i=0; i<_param._nb_bank; i++)
439	{
440	for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
441	{
442	for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port[j]; k++)
443	{
444	delete WRITE_SELECT_VAL [i][j][k];
445	delete WRITE_SELECT_ACK [i][j][k];
446	}
447	delete WRITE_SELECT_VAL [i][j];
448	delete WRITE_SELECT_ACK [i][j];
449	}
450	delete WRITE_SELECT_VAL [i];
451	delete WRITE_SELECT_ACK [i];
452	}
453	delete WRITE_SELECT_VAL;
454	delete WRITE_SELECT_ACK;
455
456	for (uint32_t i=0; i<_param._nb_bank; i++)
457	{
458	for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
459	{
460	delete WRITE_OUT_VAL [i][j];
461	delete WRITE_OUT_ACK [i][j];
462	delete WRITE_OUT_ADDRESS [i][j];
463	delete WRITE_OUT_DATA [i][j];
464	}
465
466	delete WRITE_OUT_VAL [i];
467	delete WRITE_OUT_ACK [i];
468	delete WRITE_OUT_ADDRESS [i];
469	delete WRITE_OUT_DATA [i];
470	}
471
472	delete WRITE_OUT_VAL ;
473	delete WRITE_OUT_ACK ;
474	delete WRITE_OUT_ADDRESS;
475	delete WRITE_OUT_DATA ;
476
477	#endif
478
479	delete _RegisterFile_Multi_Banked_Glue;
480	}

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