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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/src/test.cpp @ 48

Last change on this file since 48 was 44, checked in by rosiere, 17 years ago
Modification des classes d'encapsulation des interfaces. Stable sur tous les composants actuels
File size: 21.0 KB

Line
1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 16
10
11	#define TEXT(str) do {cout << "<" << name << "> : " << str << endl;} while (0)
12	#define LABEL(str) do {cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; _RegisterFile_Multi_Banked_Glue->vhdl_testbench_label(str);} while (0)
13
14	#include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/include/test.h"
15	#include "Common/include/Test.h"
16	#include "Common/include/BitManipulation.h"
17
18	void test (string name,
19	morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::Parameters _param)
20	{
21	TEXT("Simulation SystemC");
22
23	RegisterFile_Multi_Banked_Glue * _RegisterFile_Multi_Banked_Glue = new RegisterFile_Multi_Banked_Glue (name.c_str(),
24	#ifdef STATISTICS
25	morpheo::behavioural::Parameters_Statistics(5,50),
26	#endif
27	_param);
28
29	#ifdef SYSTEMC
30	/*********************************************************************
31	* Déclarations des signaux
32	*********************************************************************/
33	sc_clock * CLOCK;
34
35	sc_signal<Tcontrol_t> ** READ_IN_VAL ;
36	sc_signal<Tcontrol_t> ** READ_IN_ACK ;
37	sc_signal<Taddress_t> ** READ_IN_ADDRESS ;
38	sc_signal<Tdata_t > ** READ_IN_DATA ;
39	sc_signal<Tcontrol_t> **** READ_SELECT_VAL ;
40	sc_signal<Tcontrol_t> **** READ_SELECT_ACK ;
41	sc_signal<Tcontrol_t> *** READ_OUT_VAL ;
42	sc_signal<Tcontrol_t> *** READ_OUT_ACK ;
43	sc_signal<Taddress_t> *** READ_OUT_ADDRESS ;
44	sc_signal<Tdata_t > *** READ_OUT_DATA ;
45	sc_signal<Tcontrol_t> ** WRITE_IN_VAL ;
46	sc_signal<Tcontrol_t> ** WRITE_IN_ACK ;
47	sc_signal<Taddress_t> ** WRITE_IN_ADDRESS ;
48	sc_signal<Tdata_t > ** WRITE_IN_DATA ;
49	sc_signal<Tcontrol_t> **** WRITE_SELECT_VAL ;
50	sc_signal<Tcontrol_t> **** WRITE_SELECT_ACK ;
51	sc_signal<Tcontrol_t> *** WRITE_OUT_VAL ;
52	sc_signal<Tcontrol_t> *** WRITE_OUT_ACK ;
53	sc_signal<Taddress_t> *** WRITE_OUT_ADDRESS ;
54	sc_signal<Tdata_t > *** WRITE_OUT_DATA ;
55
56	string rename;
57
58	CLOCK = new sc_clock ("clock", 1.0, 0.5);
59
60	READ_IN_VAL = new sc_signal<Tcontrol_t> * [_param._nb_port_read];
61	READ_IN_ACK = new sc_signal<Tcontrol_t> * [_param._nb_port_read];
62	READ_IN_ADDRESS = new sc_signal<Taddress_t> * [_param._nb_port_read];
63	READ_IN_DATA = new sc_signal<Tdata_t > * [_param._nb_port_read];
64
65	for (uint32_t i=0; i<_param._nb_port_read; i++)
66	{
67	rename = "READ_IN_VAL_"+toString(i)+" ";
68	READ_IN_VAL [i] = new sc_signal<Tcontrol_t> (rename.c_str());
69	rename = "READ_IN_ACK_"+toString(i)+" ";
70	READ_IN_ACK [i] = new sc_signal<Tcontrol_t> (rename.c_str());
71	rename = "READ_IN_ADDRESS_"+toString(i)+" ";
72	READ_IN_ADDRESS [i] = new sc_signal<Taddress_t> (rename.c_str());
73	rename = "READ_IN_DATA_"+toString(i)+" ";
74	READ_IN_DATA [i] = new sc_signal<Tdata_t > (rename.c_str());
75	}
76
77	READ_SELECT_VAL = new sc_signal<Tcontrol_t> *** [_param._nb_bank];
78	READ_SELECT_ACK = new sc_signal<Tcontrol_t> *** [_param._nb_bank];
79
80	for (uint32_t i=0; i<_param._nb_bank; i++)
81	{
82	READ_SELECT_VAL [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_read_by_bank];
83	READ_SELECT_ACK [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_read_by_bank];
84
85	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
86	{
87	READ_SELECT_VAL [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_read_port [j]];
88	READ_SELECT_ACK [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_read_port [j]];
89
90	for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port [j]; k++)
91	{
92	rename="READ_SELECT_VAL_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ";
93	READ_SELECT_VAL [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str());
94
95	rename="READ_SELECT_ACK_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ";
96	READ_SELECT_ACK [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str());
97	}
98	}
99	}
100
101	READ_OUT_VAL = new sc_signal<Tcontrol_t> ** [_param._nb_bank];
102	READ_OUT_ACK = new sc_signal<Tcontrol_t> ** [_param._nb_bank];
103	READ_OUT_ADDRESS = new sc_signal<Taddress_t> ** [_param._nb_bank];
104	READ_OUT_DATA = new sc_signal<Tdata_t > ** [_param._nb_bank];
105
106	for (uint32_t i=0; i<_param._nb_bank; i++)
107	{
108	READ_OUT_VAL [i] = new sc_signal<Tcontrol_t> * [_param._nb_port_read_by_bank];
109	READ_OUT_ACK [i] = new sc_signal<Tcontrol_t> * [_param._nb_port_read_by_bank];
110	READ_OUT_ADDRESS [i] = new sc_signal<Taddress_t> * [_param._nb_port_read_by_bank];
111	READ_OUT_DATA [i] = new sc_signal<Tdata_t > * [_param._nb_port_read_by_bank];
112
113	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
114	{
115	rename="READ_OUT_VAL_"+toString(i)+"_"+toString(j)+" ";
116	READ_OUT_VAL [i][j] = new sc_signal<Tcontrol_t> (rename.c_str());
117	rename="READ_OUT_ACK_"+toString(i)+"_"+toString(j)+" ";
118	READ_OUT_ACK [i][j] = new sc_signal<Tcontrol_t> (rename.c_str());
119	rename="READ_OUT_ADDRESS_"+toString(i)+"_"+toString(j)+" ";
120	READ_OUT_ADDRESS [i][j] = new sc_signal<Taddress_t> (rename.c_str());
121	rename="READ_OUT_DATA_"+toString(i)+"_"+toString(j)+" ";
122	READ_OUT_DATA [i][j] = new sc_signal<Tdata_t > (rename.c_str());
123	}
124	}
125
126	WRITE_IN_VAL = new sc_signal<Tcontrol_t> * [_param._nb_port_write];
127	WRITE_IN_ACK = new sc_signal<Tcontrol_t> * [_param._nb_port_write];
128	WRITE_IN_ADDRESS = new sc_signal<Taddress_t> * [_param._nb_port_write];
129	WRITE_IN_DATA = new sc_signal<Tdata_t > * [_param._nb_port_write];
130	for (uint32_t i=0; i<_param._nb_port_write; i++)
131	{
132	rename = "WRITE_IN_VAL_"+toString(i)+" ";
133	WRITE_IN_VAL [i] = new sc_signal<Tcontrol_t> (rename.c_str());
134	rename = "WRITE_IN_ACK_"+toString(i)+" ";
135	WRITE_IN_ACK [i] = new sc_signal<Tcontrol_t> (rename.c_str());
136	rename = "WRITE_IN_ADDRESS_"+toString(i)+" ";
137	WRITE_IN_ADDRESS [i] = new sc_signal<Taddress_t> (rename.c_str());
138	rename = "WRITE_IN_DATA_"+toString(i)+" ";
139	WRITE_IN_DATA [i] = new sc_signal<Tdata_t > (rename.c_str());
140	}
141
142	WRITE_SELECT_VAL = new sc_signal<Tcontrol_t> *** [_param._nb_bank];
143	WRITE_SELECT_ACK = new sc_signal<Tcontrol_t> *** [_param._nb_bank];
144
145	for (uint32_t i=0; i<_param._nb_bank; i++)
146	{
147	WRITE_SELECT_VAL [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_write_by_bank];
148	WRITE_SELECT_ACK [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_write_by_bank];
149
150	for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
151	{
152	WRITE_SELECT_VAL [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_write_port [j]];
153	WRITE_SELECT_ACK [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_write_port [j]];
154
155	for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port [j]; k++)
156	{
157	rename="WRITE_SELECT_VAL_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ";
158	WRITE_SELECT_VAL [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str());
159
160	rename="WRITE_SELECT_ACK_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" ";
161	WRITE_SELECT_ACK [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str());
162	}
163	}
164	}
165
166	WRITE_OUT_VAL = new sc_signal<Tcontrol_t> ** [_param._nb_bank];
167	WRITE_OUT_ACK = new sc_signal<Tcontrol_t> ** [_param._nb_bank];
168	WRITE_OUT_ADDRESS = new sc_signal<Taddress_t> ** [_param._nb_bank];
169	WRITE_OUT_DATA = new sc_signal<Tdata_t > ** [_param._nb_bank];
170
171	for (uint32_t i=0; i<_param._nb_bank; i++)
172	{
173	WRITE_OUT_VAL [i] = new sc_signal<Tcontrol_t> * [_param._nb_port_write_by_bank];
174	WRITE_OUT_ACK [i] = new sc_signal<Tcontrol_t> * [_param._nb_port_write_by_bank];
175	WRITE_OUT_ADDRESS [i] = new sc_signal<Taddress_t> * [_param._nb_port_write_by_bank];
176	WRITE_OUT_DATA [i] = new sc_signal<Tdata_t > * [_param._nb_port_write_by_bank];
177
178	for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
179	{
180	rename = "WRITE_OUT_VAL_"+toString(i)+"_"+toString(j)+" ";
181	WRITE_OUT_VAL [i][j] = new sc_signal<Tcontrol_t> (rename.c_str());
182	rename = "WRITE_OUT_ACK_"+toString(i)+"_"+toString(j)+" ";
183	WRITE_OUT_ACK [i][j] = new sc_signal<Tcontrol_t> (rename.c_str());
184	rename = "WRITE_OUT_ADDRESS_"+toString(i)+"_"+toString(j)+" ";
185	WRITE_OUT_ADDRESS [i][j] = new sc_signal<Taddress_t> (rename.c_str());
186	rename = "WRITE_OUT_DATA_"+toString(i)+"_"+toString(j)+" ";
187	WRITE_OUT_DATA [i][j] = new sc_signal<Tdata_t > (rename.c_str());
188	}
189	}
190
191	/********************************************************
192	* Instanciation
193	********************************************************/
194
195	TEXT("Instanciation of _RegisterFile_Multi_Banked_Glue");
196
197	((_RegisterFile_Multi_Banked_Glue->in_CLOCK)) ((CLOCK));
198
199	for (uint32_t i=0; i<_param._nb_port_read; i++)
200	{
201	((_RegisterFile_Multi_Banked_Glue-> in_READ_IN_VAL [i])) ((READ_IN_VAL [i]));
202	((_RegisterFile_Multi_Banked_Glue->out_READ_IN_ACK [i])) ((READ_IN_ACK [i]));
203	((_RegisterFile_Multi_Banked_Glue-> in_READ_IN_ADDRESS [i])) ((READ_IN_ADDRESS [i]));
204	((_RegisterFile_Multi_Banked_Glue->out_READ_IN_DATA [i])) ((READ_IN_DATA [i]));
205	}
206
207	for (uint32_t i=0; i<_param._nb_bank; i++)
208	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
209	for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++)
210	{
211	((_RegisterFile_Multi_Banked_Glue->out_READ_SELECT_VAL [i][j][k])) ((READ_SELECT_VAL [i][j][k]));
212	((_RegisterFile_Multi_Banked_Glue-> in_READ_SELECT_ACK [i][j][k])) ((READ_SELECT_ACK [i][j][k]));
213	}
214
215	for (uint32_t i=0; i<_param._nb_bank; i++)
216	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
217	{
218	((_RegisterFile_Multi_Banked_Glue->out_READ_OUT_VAL [i][j])) ((READ_OUT_VAL [i][j]));
219	((_RegisterFile_Multi_Banked_Glue-> in_READ_OUT_ACK [i][j])) ((READ_OUT_ACK [i][j]));
220	((_RegisterFile_Multi_Banked_Glue->out_READ_OUT_ADDRESS [i][j])) ((READ_OUT_ADDRESS [i][j]));
221	((_RegisterFile_Multi_Banked_Glue-> in_READ_OUT_DATA [i][j])) ((READ_OUT_DATA [i][j]));
222	}
223
224	for (uint32_t i=0; i<_param._nb_port_write; i++)
225	{
226	((_RegisterFile_Multi_Banked_Glue-> in_WRITE_IN_VAL [i])) ((WRITE_IN_VAL [i]));
227	((_RegisterFile_Multi_Banked_Glue->out_WRITE_IN_ACK [i])) ((WRITE_IN_ACK [i]));
228	((_RegisterFile_Multi_Banked_Glue-> in_WRITE_IN_ADDRESS [i])) ((WRITE_IN_ADDRESS [i]));
229	((_RegisterFile_Multi_Banked_Glue-> in_WRITE_IN_DATA [i])) ((WRITE_IN_DATA [i]));
230	}
231
232	for (uint32_t i=0; i<_param._nb_bank; i++)
233	for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
234	for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port[j]; k++)
235	{
236	((_RegisterFile_Multi_Banked_Glue->out_WRITE_SELECT_VAL [i][j][k])) ((WRITE_SELECT_VAL [i][j][k]));
237	((_RegisterFile_Multi_Banked_Glue-> in_WRITE_SELECT_ACK [i][j][k])) ((WRITE_SELECT_ACK [i][j][k]));
238	}
239
240	for (uint32_t i=0; i<_param._nb_bank; i++)
241	for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
242	{
243	((_RegisterFile_Multi_Banked_Glue->out_WRITE_OUT_VAL [i][j])) ((WRITE_OUT_VAL [i][j]));
244	((_RegisterFile_Multi_Banked_Glue-> in_WRITE_OUT_ACK [i][j])) ((WRITE_OUT_ACK [i][j]));
245	((_RegisterFile_Multi_Banked_Glue->out_WRITE_OUT_ADDRESS [i][j])) ((WRITE_OUT_ADDRESS [i][j]));
246	((_RegisterFile_Multi_Banked_Glue->out_WRITE_OUT_DATA [i][j])) ((WRITE_OUT_DATA [i][j]));
247	}
248
249
250	TEXT("Start Simulation ............");
251
252	/********************************************************
253	* Simulation - Begin
254	********************************************************/
255
256	// Initialisation
257
258	const uint32_t seed = 0;
259	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
260
261	srand(seed);
262
263	sc_start(0);
264
265	LABEL("Initialisation");
266
267	uint32_t read_in_num_bank [_param._nb_port_read]; // Number of bank
268	Tcontrol_t read_is_busy [_param._nb_port_read];
269	bool read_out_find [_param._nb_bank][_param._nb_port_read_by_bank];
270	uint32_t read_out_port [_param._nb_bank][_param._nb_port_read_by_bank];
271
272	Tcontrol_t read_in_ack [_param._nb_port_read]; // to test
273	Tdata_t read_in_data [_param._nb_port_read]; // to test
274	Tcontrol_t read_out_val [_param._nb_bank][_param._nb_port_read_by_bank];
275	Taddress_t read_out_address [_param._nb_bank][_param._nb_port_read_by_bank];
276	Tcontrol_t read_select_val [_param._nb_bank][_param._nb_port_read_by_bank][_param._nb_port_read];
277
278	LABEL("Loop of Test");
279
280	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
281	{
282	LABEL("Iteration "+toString(iteration));
283
284	//LABEL("Test read_in");
285
286	// Write in interface "read_in"
287	for (uint32_t i=0; i<_param._nb_port_read; i++)
288	{
289	read_in_num_bank [i] = rand() % _param._nb_bank;
290	Tcontrol_t read_in_val = (rand() % 2) != 0;
291
292	Taddress_t address = (read_in_num_bank[i] << _param._shift_address) \| (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & i);
293
294	read_is_busy [i] = (read_in_val == 0); // invalid = busy
295	read_in_ack [i] = 0; // init
296	read_in_data [i] = 0; // init
297	READ_IN_VAL [i]->write(read_in_val); // write signal
298	READ_IN_ADDRESS [i]->write(address); // write signal
299	}
300
301	// compute the good read_select
302	for (uint32_t i=0; i<_param._nb_bank; i++)
303	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
304	{
305	Tcontrol_t read_out_ack = (rand() % 2) != 0;
306	READ_OUT_ACK [i][j]->write(read_out_ack);
307	READ_OUT_DATA [i][j]->write((j<<1)\|1); // (j<<1)\|1 afin de n'avoir jamais 0
308
309	read_out_find [i][j] = false;
310	read_out_port [i][j] = 0;
311
312	read_out_val [i][j] = 0;
313	read_out_address [i][j] = 0;
314
315	bool find = false; // have find a port_in to link with this port_out
316	for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++)
317	{
318	uint32_t num_port; // number of port
319
320	// compute the good number of port
321	if (_param._crossbar == FULL_CROSSBAR)
322	num_port = k;
323	else
324	num_port = k*_param._nb_port_read_by_bank+j;
325
326	read_select_val [i][j][k] = read_out_ack and not read_is_busy [num_port] and (read_in_num_bank[num_port] == i); // select val if port is not busy and out accept a data
327	Tcontrol_t read_select_ack = 0;
328
329	// test a previous find
330	if (not ((read_out_ack == 0) \|\| find))
331	{
332	// find a busy port?
333	find = read_select_val;
334	read_is_busy [num_port]\|= find; // port became busy if find
335	read_select_ack = find; // ack if find
336
337	if (find)
338	{
339	read_out_find [i][j] = true;
340	read_out_port [i][j] = num_port;
341
342	// know the good output
343	read_in_ack [num_port] = 1;
344	read_in_data [num_port] = ((j<<1)\|1);
345	read_out_val [i][j] = 1;
346	read_out_address [i][j] = (i << _param._shift_address) \| (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & num_port);
347	}
348	}
349
350	READ_SELECT_ACK [i][j][k]->write(read_select_ack);
351	}
352	}
353
354	// next cycle
355	sc_start(1);
356
357	// test output
358
359	TEXT ("===== Test Output =====");
360	for (uint32_t i=0; i<_param._nb_port_read; i++)
361	{
362	TEXT ("Read_in [" << i << "] : "
363	<< READ_IN_VAL [i]->read() << ","
364	<< read_in_ack [i] << " - "
365	<< "Reg[" << READ_IN_ADDRESS [i]->read() << "] -> "
366	<< read_in_data [i] << " "
367	<< "{bank : " << read_in_num_bank[i] << "}"
368	);
369
370	TEST (Tcontrol_t, read_in_ack [i], READ_IN_ACK [i]->read());
371	if (READ_IN_VAL [i]->read() and READ_IN_ACK [i]->read())
372	TEST (Tdata_t , read_in_data [i], READ_IN_DATA [i]->read());
373	}
374
375	cout << endl;
376	for (uint32_t i=0; i<_param._nb_bank; i++)
377	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
378	{
379	TEXT ("Read_out [" << i << "][" << j << "] : "
380	<< read_out_val [i][j] << ","
381	<< READ_OUT_ACK [i][j]->read() << " - "
382	<< "Reg[" << read_out_address [i][j] << "] -> "
383	<< READ_OUT_DATA [i][j]->read() << " - "
384	<< "[" << read_out_find [i][j]<< " , "
385	<< read_out_port [i][j] << "]"
386	);
387
388	TEST (Tcontrol_t, read_out_val [i][j], READ_OUT_VAL [i][j]->read());
389	if (READ_OUT_VAL [i][j]->read() and READ_OUT_ACK [i][j]->read())
390	TEST (Taddress_t, read_out_address [i][j], READ_OUT_ADDRESS [i][j]->read());
391
392	for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++)
393	{
394	uint32_t num_port; // number of port
395
396	// compute the good number of port
397	if (_param._crossbar == FULL_CROSSBAR)
398	num_port = k;
399	else
400	num_port = k*_param._nb_port_read_by_bank+j;
401
402	TEXT (" * Read_select [" << i << "][" << j << "][" << k << "] : "
403	<< read_select_val [i][j][k] << ","
404	<< READ_SELECT_ACK [i][j][k]->read() << " - "
405	<< "link with read_in[" << num_port << "]"
406	);
407
408	TEST (Tcontrol_t, read_select_val [i][j][k], READ_SELECT_VAL [i][j][k]->read());
409	}
410
411
412
413	}
414
415	}
416
417	sc_start(0);
418
419	/********************************************************
420	* Simulation - End
421	********************************************************/
422
423	TEXT("............ Stop Simulation");
424
425	delete CLOCK;
426
427	TEXT("delete read_in");
428	for (uint32_t i=0; i<_param._nb_port_read; i++)
429	{
430	// TEXT("1, i " << i);
431	delete READ_IN_VAL [i];
432	// TEXT("2");
433	delete READ_IN_ACK [i];
434	// TEXT("3");
435	delete READ_IN_ADDRESS [i];
436	// TEXT("4");
437	delete READ_IN_DATA [i];
438	// TEXT("5");
439	}
440
441	delete READ_IN_VAL ;
442	delete READ_IN_ACK ;
443	delete READ_IN_ADDRESS;
444	delete READ_IN_DATA ;
445
446	TEXT("delete read_select");
447	for (uint32_t i=0; i<_param._nb_bank; i++)
448	{
449	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
450	{
451	for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++)
452	{
453	delete READ_SELECT_VAL [i][j][k];
454	delete READ_SELECT_ACK [i][j][k];
455	}
456	delete READ_SELECT_VAL [i][j];
457	delete READ_SELECT_ACK [i][j];
458	}
459	delete READ_SELECT_VAL [i];
460	delete READ_SELECT_ACK [i];
461	}
462	delete READ_SELECT_VAL;
463	delete READ_SELECT_ACK;
464
465	TEXT("delete read_out");
466	for (uint32_t i=0; i<_param._nb_bank; i++)
467	{
468	for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++)
469	{
470	delete READ_OUT_VAL [i][j];
471	delete READ_OUT_ACK [i][j];
472	delete READ_OUT_ADDRESS [i][j];
473	delete READ_OUT_DATA [i][j];
474	}
475
476	delete READ_OUT_VAL [i];
477	delete READ_OUT_ACK [i];
478	delete READ_OUT_ADDRESS [i];
479	delete READ_OUT_DATA [i];
480	}
481
482	delete READ_OUT_VAL ;
483	delete READ_OUT_ACK ;
484	delete READ_OUT_ADDRESS;
485	delete READ_OUT_DATA ;
486
487	TEXT("delete write_in");
488	for (uint32_t i=0; i<_param._nb_port_write; i++)
489	{
490	delete WRITE_IN_VAL [i];
491	delete WRITE_IN_ACK [i];
492	delete WRITE_IN_ADDRESS [i];
493	delete WRITE_IN_DATA [i];
494	}
495
496	delete WRITE_IN_VAL ;
497	delete WRITE_IN_ACK ;
498	delete WRITE_IN_ADDRESS;
499	delete WRITE_IN_DATA ;
500
501	TEXT("delete write_select");
502	for (uint32_t i=0; i<_param._nb_bank; i++)
503	{
504	for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
505	{
506	for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port[j]; k++)
507	{
508	delete WRITE_SELECT_VAL [i][j][k];
509	delete WRITE_SELECT_ACK [i][j][k];
510	}
511	delete WRITE_SELECT_VAL [i][j];
512	delete WRITE_SELECT_ACK [i][j];
513	}
514	delete WRITE_SELECT_VAL [i];
515	delete WRITE_SELECT_ACK [i];
516	}
517	delete WRITE_SELECT_VAL;
518	delete WRITE_SELECT_ACK;
519
520	TEXT("delete write_out");
521	for (uint32_t i=0; i<_param._nb_bank; i++)
522	{
523	for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
524	{
525	delete WRITE_OUT_VAL [i][j];
526	delete WRITE_OUT_ACK [i][j];
527	delete WRITE_OUT_ADDRESS [i][j];
528	delete WRITE_OUT_DATA [i][j];
529	}
530
531	delete WRITE_OUT_VAL [i];
532	delete WRITE_OUT_ACK [i];
533	delete WRITE_OUT_ADDRESS [i];
534	delete WRITE_OUT_DATA [i];
535	}
536
537	delete WRITE_OUT_VAL ;
538	delete WRITE_OUT_ACK ;
539	delete WRITE_OUT_ADDRESS;
540	delete WRITE_OUT_DATA ;
541
542	#endif
543
544
545	delete _RegisterFile_Multi_Banked_Glue;
546	}

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