1 | /* |
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2 | * $Id$ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | * Test |
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7 | */ |
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8 | |
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9 | #define NB_ITERATION 16 |
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10 | |
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11 | #define TEXT(str) do {cout << "<" << name << "> : " << str << endl;} while (0) |
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12 | #define LABEL(str) do {cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; _RegisterFile_Multi_Banked_Glue->vhdl_testbench_label(str);} while (0) |
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13 | |
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14 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/RegisterFile_Multi_Banked_Glue/SelfTest/include/test.h" |
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15 | #include "Common/include/Test.h" |
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16 | #include "Common/include/BitManipulation.h" |
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17 | |
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18 | void test (string name, |
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19 | morpheo::behavioural::generic::registerfile::registerfile_multi_banked::registerfile_multi_banked_glue::Parameters _param) |
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20 | { |
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21 | TEXT("Simulation SystemC"); |
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22 | |
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23 | RegisterFile_Multi_Banked_Glue * _RegisterFile_Multi_Banked_Glue = new RegisterFile_Multi_Banked_Glue (name.c_str(), |
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24 | #ifdef STATISTICS |
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25 | morpheo::behavioural::Parameters_Statistics(5,50), |
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26 | #endif |
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27 | _param); |
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28 | |
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29 | #ifdef SYSTEMC |
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30 | /********************************************************************* |
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31 | * Déclarations des signaux |
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32 | *********************************************************************/ |
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33 | sc_clock * CLOCK; |
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34 | |
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35 | sc_signal<Tcontrol_t> ** READ_IN_VAL ; |
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36 | sc_signal<Tcontrol_t> ** READ_IN_ACK ; |
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37 | sc_signal<Taddress_t> ** READ_IN_ADDRESS ; |
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38 | sc_signal<Tdata_t > ** READ_IN_DATA ; |
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39 | sc_signal<Tcontrol_t> **** READ_SELECT_VAL ; |
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40 | sc_signal<Tcontrol_t> **** READ_SELECT_ACK ; |
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41 | sc_signal<Tcontrol_t> *** READ_OUT_VAL ; |
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42 | sc_signal<Tcontrol_t> *** READ_OUT_ACK ; |
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43 | sc_signal<Taddress_t> *** READ_OUT_ADDRESS ; |
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44 | sc_signal<Tdata_t > *** READ_OUT_DATA ; |
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45 | sc_signal<Tcontrol_t> ** WRITE_IN_VAL ; |
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46 | sc_signal<Tcontrol_t> ** WRITE_IN_ACK ; |
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47 | sc_signal<Taddress_t> ** WRITE_IN_ADDRESS ; |
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48 | sc_signal<Tdata_t > ** WRITE_IN_DATA ; |
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49 | sc_signal<Tcontrol_t> **** WRITE_SELECT_VAL ; |
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50 | sc_signal<Tcontrol_t> **** WRITE_SELECT_ACK ; |
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51 | sc_signal<Tcontrol_t> *** WRITE_OUT_VAL ; |
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52 | sc_signal<Tcontrol_t> *** WRITE_OUT_ACK ; |
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53 | sc_signal<Taddress_t> *** WRITE_OUT_ADDRESS ; |
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54 | sc_signal<Tdata_t > *** WRITE_OUT_DATA ; |
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55 | |
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56 | string rename; |
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57 | |
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58 | CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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59 | |
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60 | READ_IN_VAL = new sc_signal<Tcontrol_t> * [_param._nb_port_read]; |
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61 | READ_IN_ACK = new sc_signal<Tcontrol_t> * [_param._nb_port_read]; |
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62 | READ_IN_ADDRESS = new sc_signal<Taddress_t> * [_param._nb_port_read]; |
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63 | READ_IN_DATA = new sc_signal<Tdata_t > * [_param._nb_port_read]; |
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64 | |
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65 | for (uint32_t i=0; i<_param._nb_port_read; i++) |
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66 | { |
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67 | rename = "READ_IN_VAL_"+toString(i)+" "; |
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68 | READ_IN_VAL [i] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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69 | rename = "READ_IN_ACK_"+toString(i)+" "; |
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70 | READ_IN_ACK [i] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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71 | rename = "READ_IN_ADDRESS_"+toString(i)+" "; |
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72 | READ_IN_ADDRESS [i] = new sc_signal<Taddress_t> (rename.c_str()); |
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73 | rename = "READ_IN_DATA_"+toString(i)+" "; |
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74 | READ_IN_DATA [i] = new sc_signal<Tdata_t > (rename.c_str()); |
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75 | } |
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76 | |
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77 | READ_SELECT_VAL = new sc_signal<Tcontrol_t> *** [_param._nb_bank]; |
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78 | READ_SELECT_ACK = new sc_signal<Tcontrol_t> *** [_param._nb_bank]; |
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79 | |
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80 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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81 | { |
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82 | READ_SELECT_VAL [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_read_by_bank]; |
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83 | READ_SELECT_ACK [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_read_by_bank]; |
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84 | |
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85 | for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) |
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86 | { |
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87 | READ_SELECT_VAL [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_read_port [j]]; |
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88 | READ_SELECT_ACK [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_read_port [j]]; |
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89 | |
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90 | for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port [j]; k++) |
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91 | { |
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92 | rename="READ_SELECT_VAL_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" "; |
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93 | READ_SELECT_VAL [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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94 | |
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95 | rename="READ_SELECT_ACK_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" "; |
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96 | READ_SELECT_ACK [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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97 | } |
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98 | } |
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99 | } |
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100 | |
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101 | READ_OUT_VAL = new sc_signal<Tcontrol_t> ** [_param._nb_bank]; |
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102 | READ_OUT_ACK = new sc_signal<Tcontrol_t> ** [_param._nb_bank]; |
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103 | READ_OUT_ADDRESS = new sc_signal<Taddress_t> ** [_param._nb_bank]; |
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104 | READ_OUT_DATA = new sc_signal<Tdata_t > ** [_param._nb_bank]; |
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105 | |
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106 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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107 | { |
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108 | READ_OUT_VAL [i] = new sc_signal<Tcontrol_t> * [_param._nb_port_read_by_bank]; |
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109 | READ_OUT_ACK [i] = new sc_signal<Tcontrol_t> * [_param._nb_port_read_by_bank]; |
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110 | READ_OUT_ADDRESS [i] = new sc_signal<Taddress_t> * [_param._nb_port_read_by_bank]; |
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111 | READ_OUT_DATA [i] = new sc_signal<Tdata_t > * [_param._nb_port_read_by_bank]; |
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112 | |
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113 | for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) |
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114 | { |
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115 | rename="READ_OUT_VAL_"+toString(i)+"_"+toString(j)+" "; |
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116 | READ_OUT_VAL [i][j] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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117 | rename="READ_OUT_ACK_"+toString(i)+"_"+toString(j)+" "; |
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118 | READ_OUT_ACK [i][j] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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119 | rename="READ_OUT_ADDRESS_"+toString(i)+"_"+toString(j)+" "; |
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120 | READ_OUT_ADDRESS [i][j] = new sc_signal<Taddress_t> (rename.c_str()); |
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121 | rename="READ_OUT_DATA_"+toString(i)+"_"+toString(j)+" "; |
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122 | READ_OUT_DATA [i][j] = new sc_signal<Tdata_t > (rename.c_str()); |
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123 | } |
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124 | } |
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125 | |
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126 | WRITE_IN_VAL = new sc_signal<Tcontrol_t> * [_param._nb_port_write]; |
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127 | WRITE_IN_ACK = new sc_signal<Tcontrol_t> * [_param._nb_port_write]; |
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128 | WRITE_IN_ADDRESS = new sc_signal<Taddress_t> * [_param._nb_port_write]; |
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129 | WRITE_IN_DATA = new sc_signal<Tdata_t > * [_param._nb_port_write]; |
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130 | for (uint32_t i=0; i<_param._nb_port_write; i++) |
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131 | { |
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132 | rename = "WRITE_IN_VAL_"+toString(i)+" "; |
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133 | WRITE_IN_VAL [i] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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134 | rename = "WRITE_IN_ACK_"+toString(i)+" "; |
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135 | WRITE_IN_ACK [i] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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136 | rename = "WRITE_IN_ADDRESS_"+toString(i)+" "; |
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137 | WRITE_IN_ADDRESS [i] = new sc_signal<Taddress_t> (rename.c_str()); |
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138 | rename = "WRITE_IN_DATA_"+toString(i)+" "; |
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139 | WRITE_IN_DATA [i] = new sc_signal<Tdata_t > (rename.c_str()); |
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140 | } |
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141 | |
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142 | WRITE_SELECT_VAL = new sc_signal<Tcontrol_t> *** [_param._nb_bank]; |
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143 | WRITE_SELECT_ACK = new sc_signal<Tcontrol_t> *** [_param._nb_bank]; |
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144 | |
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145 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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146 | { |
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147 | WRITE_SELECT_VAL [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_write_by_bank]; |
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148 | WRITE_SELECT_ACK [i] = new sc_signal<Tcontrol_t> ** [_param._nb_port_write_by_bank]; |
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149 | |
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150 | for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) |
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151 | { |
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152 | WRITE_SELECT_VAL [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_write_port [j]]; |
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153 | WRITE_SELECT_ACK [i][j] = new sc_signal<Tcontrol_t> * [_param._nb_port_select_by_bank_write_port [j]]; |
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154 | |
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155 | for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port [j]; k++) |
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156 | { |
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157 | rename="WRITE_SELECT_VAL_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" "; |
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158 | WRITE_SELECT_VAL [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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159 | |
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160 | rename="WRITE_SELECT_ACK_"+toString(i)+"_"+toString(j)+"_"+toString(k)+" "; |
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161 | WRITE_SELECT_ACK [i][j][k] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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162 | } |
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163 | } |
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164 | } |
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165 | |
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166 | WRITE_OUT_VAL = new sc_signal<Tcontrol_t> ** [_param._nb_bank]; |
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167 | WRITE_OUT_ACK = new sc_signal<Tcontrol_t> ** [_param._nb_bank]; |
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168 | WRITE_OUT_ADDRESS = new sc_signal<Taddress_t> ** [_param._nb_bank]; |
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169 | WRITE_OUT_DATA = new sc_signal<Tdata_t > ** [_param._nb_bank]; |
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170 | |
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171 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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172 | { |
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173 | WRITE_OUT_VAL [i] = new sc_signal<Tcontrol_t> * [_param._nb_port_write_by_bank]; |
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174 | WRITE_OUT_ACK [i] = new sc_signal<Tcontrol_t> * [_param._nb_port_write_by_bank]; |
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175 | WRITE_OUT_ADDRESS [i] = new sc_signal<Taddress_t> * [_param._nb_port_write_by_bank]; |
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176 | WRITE_OUT_DATA [i] = new sc_signal<Tdata_t > * [_param._nb_port_write_by_bank]; |
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177 | |
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178 | for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) |
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179 | { |
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180 | rename = "WRITE_OUT_VAL_"+toString(i)+"_"+toString(j)+" "; |
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181 | WRITE_OUT_VAL [i][j] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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182 | rename = "WRITE_OUT_ACK_"+toString(i)+"_"+toString(j)+" "; |
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183 | WRITE_OUT_ACK [i][j] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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184 | rename = "WRITE_OUT_ADDRESS_"+toString(i)+"_"+toString(j)+" "; |
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185 | WRITE_OUT_ADDRESS [i][j] = new sc_signal<Taddress_t> (rename.c_str()); |
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186 | rename = "WRITE_OUT_DATA_"+toString(i)+"_"+toString(j)+" "; |
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187 | WRITE_OUT_DATA [i][j] = new sc_signal<Tdata_t > (rename.c_str()); |
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188 | } |
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189 | } |
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190 | |
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191 | /******************************************************** |
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192 | * Instanciation |
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193 | ********************************************************/ |
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194 | |
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195 | TEXT("Instanciation of _RegisterFile_Multi_Banked_Glue"); |
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196 | |
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197 | (*(_RegisterFile_Multi_Banked_Glue->in_CLOCK)) (*(CLOCK)); |
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198 | |
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199 | for (uint32_t i=0; i<_param._nb_port_read; i++) |
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200 | { |
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201 | (*(_RegisterFile_Multi_Banked_Glue-> in_READ_IN_VAL [i])) (*(READ_IN_VAL [i])); |
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202 | (*(_RegisterFile_Multi_Banked_Glue->out_READ_IN_ACK [i])) (*(READ_IN_ACK [i])); |
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203 | (*(_RegisterFile_Multi_Banked_Glue-> in_READ_IN_ADDRESS [i])) (*(READ_IN_ADDRESS [i])); |
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204 | (*(_RegisterFile_Multi_Banked_Glue->out_READ_IN_DATA [i])) (*(READ_IN_DATA [i])); |
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205 | } |
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206 | |
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207 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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208 | for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) |
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209 | for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++) |
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210 | { |
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211 | (*(_RegisterFile_Multi_Banked_Glue->out_READ_SELECT_VAL [i][j][k])) (*(READ_SELECT_VAL [i][j][k])); |
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212 | (*(_RegisterFile_Multi_Banked_Glue-> in_READ_SELECT_ACK [i][j][k])) (*(READ_SELECT_ACK [i][j][k])); |
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213 | } |
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214 | |
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215 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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216 | for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) |
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217 | { |
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218 | (*(_RegisterFile_Multi_Banked_Glue->out_READ_OUT_VAL [i][j])) (*(READ_OUT_VAL [i][j])); |
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219 | (*(_RegisterFile_Multi_Banked_Glue-> in_READ_OUT_ACK [i][j])) (*(READ_OUT_ACK [i][j])); |
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220 | (*(_RegisterFile_Multi_Banked_Glue->out_READ_OUT_ADDRESS [i][j])) (*(READ_OUT_ADDRESS [i][j])); |
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221 | (*(_RegisterFile_Multi_Banked_Glue-> in_READ_OUT_DATA [i][j])) (*(READ_OUT_DATA [i][j])); |
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222 | } |
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223 | |
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224 | for (uint32_t i=0; i<_param._nb_port_write; i++) |
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225 | { |
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226 | (*(_RegisterFile_Multi_Banked_Glue-> in_WRITE_IN_VAL [i])) (*(WRITE_IN_VAL [i])); |
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227 | (*(_RegisterFile_Multi_Banked_Glue->out_WRITE_IN_ACK [i])) (*(WRITE_IN_ACK [i])); |
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228 | (*(_RegisterFile_Multi_Banked_Glue-> in_WRITE_IN_ADDRESS [i])) (*(WRITE_IN_ADDRESS [i])); |
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229 | (*(_RegisterFile_Multi_Banked_Glue-> in_WRITE_IN_DATA [i])) (*(WRITE_IN_DATA [i])); |
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230 | } |
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231 | |
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232 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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233 | for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) |
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234 | for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port[j]; k++) |
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235 | { |
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236 | (*(_RegisterFile_Multi_Banked_Glue->out_WRITE_SELECT_VAL [i][j][k])) (*(WRITE_SELECT_VAL [i][j][k])); |
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237 | (*(_RegisterFile_Multi_Banked_Glue-> in_WRITE_SELECT_ACK [i][j][k])) (*(WRITE_SELECT_ACK [i][j][k])); |
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238 | } |
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239 | |
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240 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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241 | for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) |
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242 | { |
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243 | (*(_RegisterFile_Multi_Banked_Glue->out_WRITE_OUT_VAL [i][j])) (*(WRITE_OUT_VAL [i][j])); |
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244 | (*(_RegisterFile_Multi_Banked_Glue-> in_WRITE_OUT_ACK [i][j])) (*(WRITE_OUT_ACK [i][j])); |
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245 | (*(_RegisterFile_Multi_Banked_Glue->out_WRITE_OUT_ADDRESS [i][j])) (*(WRITE_OUT_ADDRESS [i][j])); |
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246 | (*(_RegisterFile_Multi_Banked_Glue->out_WRITE_OUT_DATA [i][j])) (*(WRITE_OUT_DATA [i][j])); |
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247 | } |
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248 | |
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249 | |
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250 | TEXT("Start Simulation ............"); |
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251 | |
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252 | /******************************************************** |
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253 | * Simulation - Begin |
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254 | ********************************************************/ |
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255 | |
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256 | // Initialisation |
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257 | |
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258 | const uint32_t seed = 0; |
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259 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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260 | |
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261 | srand(seed); |
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262 | |
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263 | sc_start(0); |
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264 | |
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265 | LABEL("Initialisation"); |
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266 | |
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267 | uint32_t read_in_num_bank [_param._nb_port_read]; // Number of bank |
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268 | Tcontrol_t read_is_busy [_param._nb_port_read]; |
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269 | bool read_out_find [_param._nb_bank][_param._nb_port_read_by_bank]; |
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270 | uint32_t read_out_port [_param._nb_bank][_param._nb_port_read_by_bank]; |
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271 | |
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272 | Tcontrol_t read_in_ack [_param._nb_port_read]; // to test |
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273 | Tdata_t read_in_data [_param._nb_port_read]; // to test |
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274 | Tcontrol_t read_out_val [_param._nb_bank][_param._nb_port_read_by_bank]; |
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275 | Taddress_t read_out_address [_param._nb_bank][_param._nb_port_read_by_bank]; |
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276 | Tcontrol_t read_select_val [_param._nb_bank][_param._nb_port_read_by_bank][_param._nb_port_read]; |
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277 | |
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278 | LABEL("Loop of Test"); |
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279 | |
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280 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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281 | { |
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282 | LABEL("Iteration "+toString(iteration)); |
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283 | |
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284 | //LABEL("Test read_in"); |
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285 | |
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286 | // Write in interface "read_in" |
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287 | for (uint32_t i=0; i<_param._nb_port_read; i++) |
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288 | { |
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289 | read_in_num_bank [i] = rand() % _param._nb_bank; |
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290 | Tcontrol_t read_in_val = (rand() % 2) != 0; |
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291 | |
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292 | Taddress_t address = (read_in_num_bank[i] << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & i); |
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293 | |
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294 | read_is_busy [i] = (read_in_val == 0); // invalid = busy |
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295 | read_in_ack [i] = 0; // init |
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296 | read_in_data [i] = 0; // init |
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297 | READ_IN_VAL [i]->write(read_in_val); // write signal |
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298 | READ_IN_ADDRESS [i]->write(address); // write signal |
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299 | } |
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300 | |
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301 | // compute the good read_select |
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302 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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303 | for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) |
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304 | { |
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305 | Tcontrol_t read_out_ack = (rand() % 2) != 0; |
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306 | READ_OUT_ACK [i][j]->write(read_out_ack); |
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307 | READ_OUT_DATA [i][j]->write((j<<1)|1); // (j<<1)|1 afin de n'avoir jamais 0 |
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308 | |
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309 | read_out_find [i][j] = false; |
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310 | read_out_port [i][j] = 0; |
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311 | |
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312 | read_out_val [i][j] = 0; |
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313 | read_out_address [i][j] = 0; |
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314 | |
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315 | bool find = false; // have find a port_in to link with this port_out |
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316 | for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++) |
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317 | { |
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318 | uint32_t num_port; // number of port |
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319 | |
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320 | // compute the good number of port |
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321 | if (_param._crossbar == FULL_CROSSBAR) |
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322 | num_port = k; |
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323 | else |
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324 | num_port = k*_param._nb_port_read_by_bank+j; |
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325 | |
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326 | read_select_val [i][j][k] = read_out_ack and not read_is_busy [num_port] and (read_in_num_bank[num_port] == i); // select val if port is not busy and out accept a data |
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327 | Tcontrol_t read_select_ack = 0; |
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328 | |
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329 | // test a previous find |
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330 | if (not ((read_out_ack == 0) || find)) |
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331 | { |
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332 | // find a busy port? |
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333 | find = read_select_val; |
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334 | read_is_busy [num_port]|= find; // port became busy if find |
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335 | read_select_ack = find; // ack if find |
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336 | |
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337 | if (find) |
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338 | { |
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339 | read_out_find [i][j] = true; |
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340 | read_out_port [i][j] = num_port; |
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341 | |
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342 | // know the good output |
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343 | read_in_ack [num_port] = 1; |
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344 | read_in_data [num_port] = ((j<<1)|1); |
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345 | read_out_val [i][j] = 1; |
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346 | read_out_address [i][j] = (i << _param._shift_address) | (gen_mask<Taddress_t>(_param._size_address-_param._shift_address) & num_port); |
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347 | } |
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348 | } |
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349 | |
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350 | READ_SELECT_ACK [i][j][k]->write(read_select_ack); |
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351 | } |
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352 | } |
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353 | |
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354 | // next cycle |
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355 | sc_start(1); |
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356 | |
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357 | // test output |
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358 | |
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359 | TEXT ("===== Test Output ====="); |
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360 | for (uint32_t i=0; i<_param._nb_port_read; i++) |
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361 | { |
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362 | TEXT ("Read_in [" << i << "] : " |
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363 | << READ_IN_VAL [i]->read() << "," |
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364 | << read_in_ack [i] << " - " |
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365 | << "Reg[" << READ_IN_ADDRESS [i]->read() << "] -> " |
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366 | << read_in_data [i] << " " |
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367 | << "{bank : " << read_in_num_bank[i] << "}" |
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368 | ); |
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369 | |
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370 | TEST (Tcontrol_t, read_in_ack [i], READ_IN_ACK [i]->read()); |
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371 | if (READ_IN_VAL [i]->read() and READ_IN_ACK [i]->read()) |
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372 | TEST (Tdata_t , read_in_data [i], READ_IN_DATA [i]->read()); |
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373 | } |
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374 | |
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375 | cout << endl; |
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376 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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377 | for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) |
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378 | { |
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379 | TEXT ("Read_out [" << i << "][" << j << "] : " |
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380 | << read_out_val [i][j] << "," |
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381 | << READ_OUT_ACK [i][j]->read() << " - " |
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382 | << "Reg[" << read_out_address [i][j] << "] -> " |
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383 | << READ_OUT_DATA [i][j]->read() << " - " |
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384 | << "[" << read_out_find [i][j]<< " , " |
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385 | << read_out_port [i][j] << "]" |
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386 | ); |
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387 | |
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388 | TEST (Tcontrol_t, read_out_val [i][j], READ_OUT_VAL [i][j]->read()); |
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389 | if (READ_OUT_VAL [i][j]->read() and READ_OUT_ACK [i][j]->read()) |
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390 | TEST (Taddress_t, read_out_address [i][j], READ_OUT_ADDRESS [i][j]->read()); |
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391 | |
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392 | for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++) |
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393 | { |
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394 | uint32_t num_port; // number of port |
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395 | |
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396 | // compute the good number of port |
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397 | if (_param._crossbar == FULL_CROSSBAR) |
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398 | num_port = k; |
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399 | else |
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400 | num_port = k*_param._nb_port_read_by_bank+j; |
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401 | |
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402 | TEXT (" * Read_select [" << i << "][" << j << "][" << k << "] : " |
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403 | << read_select_val [i][j][k] << "," |
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404 | << READ_SELECT_ACK [i][j][k]->read() << " - " |
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405 | << "link with read_in[" << num_port << "]" |
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406 | ); |
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407 | |
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408 | TEST (Tcontrol_t, read_select_val [i][j][k], READ_SELECT_VAL [i][j][k]->read()); |
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409 | } |
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410 | |
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411 | |
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412 | |
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413 | } |
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414 | |
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415 | } |
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416 | |
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417 | sc_start(0); |
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418 | |
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419 | /******************************************************** |
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420 | * Simulation - End |
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421 | ********************************************************/ |
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422 | |
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423 | TEXT("............ Stop Simulation"); |
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424 | |
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425 | delete CLOCK; |
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426 | |
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427 | TEXT("delete read_in"); |
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428 | for (uint32_t i=0; i<_param._nb_port_read; i++) |
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429 | { |
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430 | // TEXT("1, i " << i); |
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431 | delete READ_IN_VAL [i]; |
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432 | // TEXT("2"); |
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433 | delete READ_IN_ACK [i]; |
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434 | // TEXT("3"); |
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435 | delete READ_IN_ADDRESS [i]; |
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436 | // TEXT("4"); |
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437 | delete READ_IN_DATA [i]; |
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438 | // TEXT("5"); |
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439 | } |
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440 | |
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441 | delete READ_IN_VAL ; |
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442 | delete READ_IN_ACK ; |
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443 | delete READ_IN_ADDRESS; |
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444 | delete READ_IN_DATA ; |
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445 | |
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446 | TEXT("delete read_select"); |
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447 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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448 | { |
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449 | for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) |
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450 | { |
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451 | for (uint32_t k=0; k<_param._nb_port_select_by_bank_read_port[j]; k++) |
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452 | { |
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453 | delete READ_SELECT_VAL [i][j][k]; |
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454 | delete READ_SELECT_ACK [i][j][k]; |
---|
455 | } |
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456 | delete READ_SELECT_VAL [i][j]; |
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457 | delete READ_SELECT_ACK [i][j]; |
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458 | } |
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459 | delete READ_SELECT_VAL [i]; |
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460 | delete READ_SELECT_ACK [i]; |
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461 | } |
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462 | delete READ_SELECT_VAL; |
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463 | delete READ_SELECT_ACK; |
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464 | |
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465 | TEXT("delete read_out"); |
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466 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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467 | { |
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468 | for (uint32_t j=0; j<_param._nb_port_read_by_bank; j++) |
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469 | { |
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470 | delete READ_OUT_VAL [i][j]; |
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471 | delete READ_OUT_ACK [i][j]; |
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472 | delete READ_OUT_ADDRESS [i][j]; |
---|
473 | delete READ_OUT_DATA [i][j]; |
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474 | } |
---|
475 | |
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476 | delete READ_OUT_VAL [i]; |
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477 | delete READ_OUT_ACK [i]; |
---|
478 | delete READ_OUT_ADDRESS [i]; |
---|
479 | delete READ_OUT_DATA [i]; |
---|
480 | } |
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481 | |
---|
482 | delete READ_OUT_VAL ; |
---|
483 | delete READ_OUT_ACK ; |
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484 | delete READ_OUT_ADDRESS; |
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485 | delete READ_OUT_DATA ; |
---|
486 | |
---|
487 | TEXT("delete write_in"); |
---|
488 | for (uint32_t i=0; i<_param._nb_port_write; i++) |
---|
489 | { |
---|
490 | delete WRITE_IN_VAL [i]; |
---|
491 | delete WRITE_IN_ACK [i]; |
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492 | delete WRITE_IN_ADDRESS [i]; |
---|
493 | delete WRITE_IN_DATA [i]; |
---|
494 | } |
---|
495 | |
---|
496 | delete WRITE_IN_VAL ; |
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497 | delete WRITE_IN_ACK ; |
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498 | delete WRITE_IN_ADDRESS; |
---|
499 | delete WRITE_IN_DATA ; |
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500 | |
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501 | TEXT("delete write_select"); |
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502 | for (uint32_t i=0; i<_param._nb_bank; i++) |
---|
503 | { |
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504 | for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) |
---|
505 | { |
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506 | for (uint32_t k=0; k<_param._nb_port_select_by_bank_write_port[j]; k++) |
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507 | { |
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508 | delete WRITE_SELECT_VAL [i][j][k]; |
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509 | delete WRITE_SELECT_ACK [i][j][k]; |
---|
510 | } |
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511 | delete WRITE_SELECT_VAL [i][j]; |
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512 | delete WRITE_SELECT_ACK [i][j]; |
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513 | } |
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514 | delete WRITE_SELECT_VAL [i]; |
---|
515 | delete WRITE_SELECT_ACK [i]; |
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516 | } |
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517 | delete WRITE_SELECT_VAL; |
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518 | delete WRITE_SELECT_ACK; |
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519 | |
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520 | TEXT("delete write_out"); |
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521 | for (uint32_t i=0; i<_param._nb_bank; i++) |
---|
522 | { |
---|
523 | for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++) |
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524 | { |
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525 | delete WRITE_OUT_VAL [i][j]; |
---|
526 | delete WRITE_OUT_ACK [i][j]; |
---|
527 | delete WRITE_OUT_ADDRESS [i][j]; |
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528 | delete WRITE_OUT_DATA [i][j]; |
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529 | } |
---|
530 | |
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531 | delete WRITE_OUT_VAL [i]; |
---|
532 | delete WRITE_OUT_ACK [i]; |
---|
533 | delete WRITE_OUT_ADDRESS [i]; |
---|
534 | delete WRITE_OUT_DATA [i]; |
---|
535 | } |
---|
536 | |
---|
537 | delete WRITE_OUT_VAL ; |
---|
538 | delete WRITE_OUT_ACK ; |
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539 | delete WRITE_OUT_ADDRESS; |
---|
540 | delete WRITE_OUT_DATA ; |
---|
541 | |
---|
542 | #endif |
---|
543 | |
---|
544 | |
---|
545 | delete _RegisterFile_Multi_Banked_Glue; |
---|
546 | } |
---|