source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/mkf.info @ 138

Last change on this file since 138 was 138, checked in by rosiere, 14 years ago

1) add counters_t type for interface
2) fix in check load in load_store_unit
3) add parameters (but not yet implemented)
4) change environment and add script (distcc_env.sh ...)
5) add warning if an unser change rename flag with l.mtspr instruction
6) ...
  • Property svn:keywords set to Id
File size: 5.9 KB
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1
2# RegisterFile_Multi_Banked_00
3target_dep      all     RegisterFile_Multi_Banked_00.ngc
4target_dep      RegisterFile_Multi_Banked_00.ngc        RegisterFile_Multi_Banked_00.prj
5target_dep      RegisterFile_Multi_Banked_00.prj        RegisterFile_Multi_Banked_00_bank_Pack.vhdl RegisterFile_Multi_Banked_00_bank.vhdl RegisterFile_Multi_Banked_00_Pack.vhdl RegisterFile_Multi_Banked_00_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_00_select_3_ports.vhdl RegisterFile_Multi_Banked_00.vhdl
6
7# RegisterFile_Multi_Banked_01
8target_dep      all     RegisterFile_Multi_Banked_01.ngc
9target_dep      RegisterFile_Multi_Banked_01.ngc        RegisterFile_Multi_Banked_01.prj
10target_dep      RegisterFile_Multi_Banked_01.prj        RegisterFile_Multi_Banked_01_bank_Pack.vhdl RegisterFile_Multi_Banked_01_bank.vhdl RegisterFile_Multi_Banked_01_Pack.vhdl RegisterFile_Multi_Banked_01_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_01_select_3_ports.vhdl RegisterFile_Multi_Banked_01.vhdl
11
12# RegisterFile_Multi_Banked_02
13target_dep      all     RegisterFile_Multi_Banked_02.ngc
14target_dep      RegisterFile_Multi_Banked_02.ngc        RegisterFile_Multi_Banked_02.prj
15target_dep      RegisterFile_Multi_Banked_02.prj        RegisterFile_Multi_Banked_02_bank_Pack.vhdl RegisterFile_Multi_Banked_02_bank.vhdl RegisterFile_Multi_Banked_02_Pack.vhdl RegisterFile_Multi_Banked_02_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_02_select_4_ports.vhdl RegisterFile_Multi_Banked_02.vhdl
16
17# RegisterFile_Multi_Banked_03
18target_dep      all     RegisterFile_Multi_Banked_03.ngc
19target_dep      RegisterFile_Multi_Banked_03.ngc        RegisterFile_Multi_Banked_03.prj
20target_dep      RegisterFile_Multi_Banked_03.prj        RegisterFile_Multi_Banked_03_bank_Pack.vhdl RegisterFile_Multi_Banked_03_bank.vhdl RegisterFile_Multi_Banked_03_Pack.vhdl RegisterFile_Multi_Banked_03_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_03_select_4_ports.vhdl RegisterFile_Multi_Banked_03.vhdl
21
22# RegisterFile_Multi_Banked_04
23target_dep      all     RegisterFile_Multi_Banked_04.ngc
24target_dep      RegisterFile_Multi_Banked_04.ngc        RegisterFile_Multi_Banked_04.prj
25target_dep      RegisterFile_Multi_Banked_04.prj        RegisterFile_Multi_Banked_04_bank_Pack.vhdl RegisterFile_Multi_Banked_04_bank.vhdl RegisterFile_Multi_Banked_04_Pack.vhdl RegisterFile_Multi_Banked_04_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_04_select_6_ports.vhdl RegisterFile_Multi_Banked_04.vhdl
26
27# RegisterFile_Multi_Banked_05
28target_dep      all     RegisterFile_Multi_Banked_05.ngc
29target_dep      RegisterFile_Multi_Banked_05.ngc        RegisterFile_Multi_Banked_05.prj
30target_dep      RegisterFile_Multi_Banked_05.prj        RegisterFile_Multi_Banked_05_bank_Pack.vhdl RegisterFile_Multi_Banked_05_bank.vhdl RegisterFile_Multi_Banked_05_Pack.vhdl RegisterFile_Multi_Banked_05_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_05_select_2_ports.vhdl RegisterFile_Multi_Banked_05.vhdl
31
32# RegisterFile_Multi_Banked_06
33target_dep      all     RegisterFile_Multi_Banked_06.ngc
34target_dep      RegisterFile_Multi_Banked_06.ngc        RegisterFile_Multi_Banked_06.prj
35target_dep      RegisterFile_Multi_Banked_06.prj        RegisterFile_Multi_Banked_06_bank_Pack.vhdl RegisterFile_Multi_Banked_06_bank.vhdl RegisterFile_Multi_Banked_06_Pack.vhdl RegisterFile_Multi_Banked_06_select_6_ports_Pack.vhdl RegisterFile_Multi_Banked_06_select_6_ports.vhdl RegisterFile_Multi_Banked_06.vhdl
36
37# RegisterFile_Multi_Banked_07
38target_dep      all     RegisterFile_Multi_Banked_07.ngc
39target_dep      RegisterFile_Multi_Banked_07.ngc        RegisterFile_Multi_Banked_07.prj
40target_dep      RegisterFile_Multi_Banked_07.prj        RegisterFile_Multi_Banked_07_bank_Pack.vhdl RegisterFile_Multi_Banked_07_bank.vhdl RegisterFile_Multi_Banked_07_Pack.vhdl RegisterFile_Multi_Banked_07_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_1_ports.vhdl RegisterFile_Multi_Banked_07_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_07_select_2_ports.vhdl RegisterFile_Multi_Banked_07.vhdl
41
42# RegisterFile_Multi_Banked_08
43target_dep      all     RegisterFile_Multi_Banked_08.ngc
44target_dep      RegisterFile_Multi_Banked_08.ngc        RegisterFile_Multi_Banked_08.prj
45target_dep      RegisterFile_Multi_Banked_08.prj        RegisterFile_Multi_Banked_08_bank_Pack.vhdl RegisterFile_Multi_Banked_08_bank.vhdl RegisterFile_Multi_Banked_08_Pack.vhdl RegisterFile_Multi_Banked_08_select_11_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_11_ports.vhdl RegisterFile_Multi_Banked_08_select_22_ports_Pack.vhdl RegisterFile_Multi_Banked_08_select_22_ports.vhdl RegisterFile_Multi_Banked_08.vhdl
46
47# RegisterFile_Multi_Banked_09
48target_dep      all     RegisterFile_Multi_Banked_09.ngc
49target_dep      RegisterFile_Multi_Banked_09.ngc        RegisterFile_Multi_Banked_09.prj
50target_dep      RegisterFile_Multi_Banked_09.prj        RegisterFile_Multi_Banked_09_bank_Pack.vhdl RegisterFile_Multi_Banked_09_bank.vhdl RegisterFile_Multi_Banked_09_Pack.vhdl RegisterFile_Multi_Banked_09_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_2_ports.vhdl RegisterFile_Multi_Banked_09_select_3_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_3_ports.vhdl RegisterFile_Multi_Banked_09_select_4_ports_Pack.vhdl RegisterFile_Multi_Banked_09_select_4_ports.vhdl RegisterFile_Multi_Banked_09.vhdl
51
52# RegisterFile_Multi_Banked_10
53target_dep      all     RegisterFile_Multi_Banked_10.ngc
54target_dep      RegisterFile_Multi_Banked_10.ngc        RegisterFile_Multi_Banked_10.prj
55target_dep      RegisterFile_Multi_Banked_10.prj        RegisterFile_Multi_Banked_10_bank_Pack.vhdl RegisterFile_Multi_Banked_10_bank.vhdl RegisterFile_Multi_Banked_10_Pack.vhdl RegisterFile_Multi_Banked_10_select_11_ports_Pack.vhdl RegisterFile_Multi_Banked_10_select_11_ports.vhdl RegisterFile_Multi_Banked_10.vhdl
56
57# RegisterFile_Multi_Banked_11
58target_dep      all     RegisterFile_Multi_Banked_11.ngc
59target_dep      RegisterFile_Multi_Banked_11.ngc        RegisterFile_Multi_Banked_11.prj
60target_dep      RegisterFile_Multi_Banked_11.prj        RegisterFile_Multi_Banked_11_bank_Pack.vhdl RegisterFile_Multi_Banked_11_bank.vhdl RegisterFile_Multi_Banked_11_Pack.vhdl RegisterFile_Multi_Banked_11_select_1_ports_Pack.vhdl RegisterFile_Multi_Banked_11_select_1_ports.vhdl RegisterFile_Multi_Banked_11_select_2_ports_Pack.vhdl RegisterFile_Multi_Banked_11_select_2_ports.vhdl RegisterFile_Multi_Banked_11.vhdl
61
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