[10] | 1 | /* |
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| 2 | * $Id$ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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| 9 | #define NB_ITERATION 1 |
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| 10 | |
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[15] | 11 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/include/test.h" |
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[10] | 12 | #include "Include/Test.h" |
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| 13 | |
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| 14 | void test (string name, |
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[15] | 15 | morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters _param) |
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[10] | 16 | { |
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| 17 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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| 18 | |
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| 19 | RegisterFile_Multi_Banked * _RegisterFile_Multi_Banked = new RegisterFile_Multi_Banked (name.c_str(), |
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| 20 | #ifdef STATISTICS |
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| 21 | morpheo::behavioural::Parameters_Statistics(5,50), |
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| 22 | #endif |
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| 23 | _param); |
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| 24 | |
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| 25 | #ifdef SYSTEMC |
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| 26 | /********************************************************************* |
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| 27 | * Déclarations des signaux |
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| 28 | *********************************************************************/ |
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| 29 | sc_clock * CLOCK; |
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| 30 | sc_signal<Tcontrol_t> * NRESET ; |
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| 31 | |
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| 32 | // ----- Interface Read |
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| 33 | sc_signal<Tcontrol_t> ** READ_VAL ; |
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| 34 | sc_signal<Tcontrol_t> ** READ_ACK ; |
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| 35 | sc_signal<Taddress_t> ** READ_ADDRESS ; |
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| 36 | sc_signal<Tdata_t> ** READ_DATA ; |
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| 37 | |
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| 38 | // ----- Interface Write |
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| 39 | sc_signal<Tcontrol_t> ** WRITE_VAL ; |
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| 40 | sc_signal<Tcontrol_t> ** WRITE_ACK ; |
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| 41 | sc_signal<Taddress_t> ** WRITE_ADDRESS; |
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| 42 | sc_signal<Tdata_t> ** WRITE_DATA ; |
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| 43 | |
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| 44 | string rename; |
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| 45 | |
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| 46 | CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 47 | |
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| 48 | NRESET = new sc_signal<Tcontrol_t> ("in_NRESET"); |
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| 49 | |
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| 50 | // ----- Interface Read |
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| 51 | READ_VAL = new sc_signal<Tcontrol_t> * [_param._nb_port_read]; |
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| 52 | READ_ACK = new sc_signal<Tcontrol_t> * [_param._nb_port_read]; |
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| 53 | READ_ADDRESS = new sc_signal<Taddress_t> * [_param._nb_port_read]; |
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| 54 | READ_DATA = new sc_signal<Tdata_t> * [_param._nb_port_read]; |
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| 55 | |
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| 56 | for (uint32_t i=0; i<_param._nb_port_read; i++) |
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| 57 | { |
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| 58 | rename = "READ_VAL_" +toString(i); |
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| 59 | READ_VAL [i] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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| 60 | rename = "READ_ACK_" +toString(i); |
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| 61 | READ_ACK [i] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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| 62 | rename = "READ_ADDRESS_"+toString(i); |
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| 63 | READ_ADDRESS [i] = new sc_signal<Taddress_t> (rename.c_str()); |
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| 64 | rename = "READ_DATA_" +toString(i); |
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| 65 | READ_DATA [i] = new sc_signal<Tdata_t> (rename.c_str()); |
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| 66 | } |
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| 67 | |
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| 68 | // ----- Interface Write |
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| 69 | WRITE_VAL = new sc_signal<Tcontrol_t> * [_param._nb_port_write]; |
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| 70 | WRITE_ACK = new sc_signal<Tcontrol_t> * [_param._nb_port_write]; |
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| 71 | WRITE_ADDRESS = new sc_signal<Taddress_t> * [_param._nb_port_write]; |
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| 72 | WRITE_DATA = new sc_signal<Tdata_t> * [_param._nb_port_write]; |
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| 73 | |
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| 74 | for (uint32_t i=0; i<_param._nb_port_write; i++) |
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| 75 | { |
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| 76 | rename = "WRITE_VAL_" +toString(i); |
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| 77 | WRITE_VAL [i] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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| 78 | rename = "WRITE_ACK_" +toString(i); |
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| 79 | WRITE_ACK [i] = new sc_signal<Tcontrol_t> (rename.c_str()); |
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| 80 | rename = "WRITE_ADDRESS_"+toString(i); |
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| 81 | WRITE_ADDRESS [i] = new sc_signal<Taddress_t> (rename.c_str()); |
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| 82 | rename = "WRITE_DATA_" +toString(i); |
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| 83 | WRITE_DATA [i] = new sc_signal<Tdata_t> (rename.c_str()); |
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| 84 | } |
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| 85 | |
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| 86 | /******************************************************** |
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| 87 | * Instanciation |
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| 88 | ********************************************************/ |
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| 89 | |
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| 90 | cout << "<" << name << "> Instanciation of _RegisterFile_Multi_Banked" << endl; |
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| 91 | |
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| 92 | (*(_RegisterFile_Multi_Banked->in_CLOCK )) (*(CLOCK )); |
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| 93 | (*(_RegisterFile_Multi_Banked->in_NRESET)) (*(NRESET)); |
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| 94 | |
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| 95 | for (uint32_t i=0; i<_param._nb_port_read; i++) |
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| 96 | { |
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| 97 | (*(_RegisterFile_Multi_Banked-> in_READ_VAL [i])) (*(READ_VAL [i])); |
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| 98 | (*(_RegisterFile_Multi_Banked->out_READ_ACK [i])) (*(READ_ACK [i])); |
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| 99 | (*(_RegisterFile_Multi_Banked-> in_READ_ADDRESS [i])) (*(READ_ADDRESS [i])); |
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| 100 | (*(_RegisterFile_Multi_Banked->out_READ_DATA [i])) (*(READ_DATA [i])); |
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| 101 | } |
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| 102 | for (uint32_t i=0; i<_param._nb_port_write; i++) |
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| 103 | { |
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| 104 | (*(_RegisterFile_Multi_Banked-> in_WRITE_VAL [i])) (*(WRITE_VAL [i])); |
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| 105 | (*(_RegisterFile_Multi_Banked->out_WRITE_ACK [i])) (*(WRITE_ACK [i])); |
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| 106 | (*(_RegisterFile_Multi_Banked-> in_WRITE_ADDRESS [i])) (*(WRITE_ADDRESS [i])); |
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| 107 | (*(_RegisterFile_Multi_Banked-> in_WRITE_DATA [i])) (*(WRITE_DATA [i])); |
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| 108 | } |
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| 109 | |
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| 110 | /******************************************************** |
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| 111 | * Simulation - Begin |
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| 112 | ********************************************************/ |
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| 113 | |
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| 114 | cout << "<" << name << "> Start Simulation ............" << endl; |
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| 115 | // Initialisation |
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| 116 | |
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| 117 | const uint32_t seed = 0; |
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| 118 | //const uint32_t seed = static_cast<uint32_t>(time(NULL)); |
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| 119 | |
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| 120 | srand(seed); |
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| 121 | |
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| 122 | sc_start(0); |
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| 123 | _RegisterFile_Multi_Banked->vhdl_testbench_label("Initialisation"); |
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| 124 | cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl; |
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| 125 | |
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| 126 | |
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| 127 | _RegisterFile_Multi_Banked->vhdl_testbench_label("Loop of Test"); |
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| 128 | cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl; |
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| 129 | |
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| 130 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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| 131 | { |
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| 132 | _RegisterFile_Multi_Banked->vhdl_testbench_label("Iteration "+toString(iteration)); |
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| 133 | |
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| 134 | sc_start(1); |
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| 135 | } |
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| 136 | |
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| 137 | /******************************************************** |
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| 138 | * Simulation - End |
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| 139 | ********************************************************/ |
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| 140 | |
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| 141 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
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| 142 | |
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| 143 | delete CLOCK; |
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| 144 | delete NRESET; |
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| 145 | |
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| 146 | // ----- Interface Read |
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| 147 | for (uint32_t i=0; i<_param._nb_port_read; i++) |
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| 148 | { |
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| 149 | delete READ_VAL [i]; |
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| 150 | delete READ_ACK [i]; |
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| 151 | delete READ_ADDRESS [i]; |
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| 152 | delete READ_DATA [i]; |
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| 153 | } |
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| 154 | |
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| 155 | delete READ_VAL ; |
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| 156 | delete READ_ACK ; |
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| 157 | delete READ_ADDRESS; |
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| 158 | delete READ_DATA ; |
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| 159 | |
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| 160 | // ----- Interface Write |
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| 161 | for (uint32_t i=0; i<_param._nb_port_write; i++) |
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| 162 | { |
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| 163 | delete WRITE_VAL [i]; |
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| 164 | delete WRITE_ACK [i]; |
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| 165 | delete WRITE_ADDRESS [i]; |
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| 166 | delete WRITE_DATA [i]; |
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| 167 | } |
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| 168 | |
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| 169 | delete WRITE_VAL ; |
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| 170 | delete WRITE_ACK ; |
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| 171 | delete WRITE_ADDRESS; |
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| 172 | delete WRITE_DATA ; |
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| 173 | |
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| 174 | #endif |
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| 175 | |
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| 176 | delete _RegisterFile_Multi_Banked; |
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| 177 | } |
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