[53] | 1 | /* |
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| 2 | * $Id: test.cpp 82 2008-05-01 16:48:45Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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[57] | 9 | #define NB_ITERATION 1 |
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| 10 | #define CYCLE_MAX (10240*NB_ITERATION) |
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[53] | 11 | |
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| 12 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/SelfTest/include/test.h" |
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| 13 | #include "Common/include/Test.h" |
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| 14 | |
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| 15 | void test (string name, |
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| 16 | morpheo::behavioural::generic::registerfile::registerfile_multi_banked::Parameters * _param) |
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| 17 | { |
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| 18 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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| 19 | |
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[57] | 20 | |
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| 21 | #ifdef STATISTICS |
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| 22 | morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics(5,50); |
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| 23 | #endif |
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| 24 | |
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[82] | 25 | RegisterFile_Multi_Banked * _RegisterFile_Multi_Banked = new RegisterFile_Multi_Banked |
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| 26 | (name.c_str(), |
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[53] | 27 | #ifdef STATISTICS |
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[82] | 28 | _param_stat, |
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[53] | 29 | #endif |
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[82] | 30 | _param, |
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| 31 | USE_ALL); |
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[53] | 32 | |
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| 33 | #ifdef SYSTEMC |
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| 34 | /********************************************************************* |
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| 35 | * Déclarations des signaux |
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| 36 | *********************************************************************/ |
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| 37 | sc_clock * CLOCK; |
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| 38 | sc_signal<Tcontrol_t> * NRESET; |
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| 39 | |
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| 40 | sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read]; |
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| 41 | sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read]; |
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| 42 | sc_signal<Taddress_t> READ_ADDRESS [_param->_nb_port_read]; |
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| 43 | sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read]; |
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| 44 | |
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| 45 | sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write]; |
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| 46 | sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write]; |
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| 47 | sc_signal<Taddress_t> WRITE_ADDRESS [_param->_nb_port_write]; |
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| 48 | sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write]; |
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| 49 | |
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| 50 | string rename; |
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| 51 | |
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| 52 | CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 53 | NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 54 | |
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| 55 | /******************************************************** |
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| 56 | * Instanciation |
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| 57 | ********************************************************/ |
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| 58 | |
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| 59 | cout << "<" << name << "> Instanciation of _RegisterFile_Multi_Banked" << endl; |
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| 60 | |
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| 61 | (*(_RegisterFile_Multi_Banked->in_CLOCK)) (*(CLOCK)); |
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| 62 | (*(_RegisterFile_Multi_Banked->in_NRESET)) (*(NRESET)); |
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| 63 | |
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| 64 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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| 65 | { |
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| 66 | (*(_RegisterFile_Multi_Banked-> in_READ_VAL [i])) (READ_VAL [i]); |
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| 67 | (*(_RegisterFile_Multi_Banked->out_READ_ACK [i])) (READ_ACK [i]); |
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[62] | 68 | if (_param->_have_port_address==true) |
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[53] | 69 | (*(_RegisterFile_Multi_Banked-> in_READ_ADDRESS [i])) (READ_ADDRESS [i]); |
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| 70 | (*(_RegisterFile_Multi_Banked->out_READ_DATA [i])) (READ_DATA [i]); |
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| 71 | } |
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| 72 | |
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| 73 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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| 74 | { |
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| 75 | (*(_RegisterFile_Multi_Banked-> in_WRITE_VAL [i])) (WRITE_VAL [i]); |
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| 76 | (*(_RegisterFile_Multi_Banked->out_WRITE_ACK [i])) (WRITE_ACK [i]); |
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[62] | 77 | if (_param->_have_port_address==true) |
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[53] | 78 | (*(_RegisterFile_Multi_Banked-> in_WRITE_ADDRESS [i])) (WRITE_ADDRESS [i]); |
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| 79 | (*(_RegisterFile_Multi_Banked-> in_WRITE_DATA [i])) (WRITE_DATA [i]); |
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| 80 | } |
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| 81 | |
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| 82 | cout << "<" << name << "> Start Simulation ............" << endl; |
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| 83 | Time * _time = new Time(); |
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| 84 | |
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| 85 | /******************************************************** |
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| 86 | * Simulation - Begin |
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| 87 | ********************************************************/ |
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| 88 | const uint32_t nb_request = _param->_nb_word; |
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| 89 | // random init |
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| 90 | const uint32_t grain = 0; |
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| 91 | //const uint32_t grain = static_cast<uint32_t>(time(NULL)); |
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| 92 | |
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| 93 | srand(grain); |
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| 94 | |
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| 95 | // Initialisation |
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| 96 | |
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| 97 | SC_START(0); |
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| 98 | |
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| 99 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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| 100 | WRITE_VAL [i] .write (0); |
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| 101 | |
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| 102 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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| 103 | READ_VAL [i] .write (0); |
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| 104 | |
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| 105 | NRESET->write(0); |
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| 106 | |
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| 107 | SC_START(5); |
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| 108 | |
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| 109 | NRESET->write(1); |
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| 110 | |
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| 111 | for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++) |
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| 112 | { |
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| 113 | cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl; |
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| 114 | |
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| 115 | Taddress_t nb_val = 0; |
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| 116 | Taddress_t nb_ack = 0; |
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| 117 | |
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| 118 | Tdata_t tab_data [_param->_nb_word]; |
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| 119 | Taddress_t tab_address [nb_request ]; |
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| 120 | |
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| 121 | for (uint32_t i=0; i<_param->_nb_word; i++) |
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| 122 | tab_data [i]= rand()%(1<<(_param->_size_word-1)); |
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| 123 | for (uint32_t i=0; i<nb_request; i++) |
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| 124 | tab_address [i]= rand()%(1<<(_param->_size_address)); |
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| 125 | |
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| 126 | while (nb_ack < nb_request) |
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| 127 | { |
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| 128 | cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; |
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| 129 | |
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| 130 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
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| 131 | { |
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| 132 | if ((nb_val < nb_request) and |
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| 133 | (WRITE_VAL [num_port].read() == 0)) |
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| 134 | { |
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| 135 | cout << "(" << num_port << ") [" << tab_address[nb_val] << "] <= " << tab_data[tab_address[nb_val]] << endl; |
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| 136 | |
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| 137 | WRITE_VAL [num_port] .write(1); |
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| 138 | WRITE_DATA [num_port] .write(tab_data[tab_address[nb_val]]); |
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| 139 | WRITE_ADDRESS [num_port] .write(tab_address[nb_val]); |
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| 140 | |
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| 141 | nb_val ++; |
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| 142 | |
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| 143 | // Address can be not a multiple of nb_port_write |
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| 144 | if (nb_val >= nb_request) |
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| 145 | break; |
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| 146 | } |
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| 147 | } |
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| 148 | |
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| 149 | SC_START(1); |
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| 150 | |
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| 151 | // reset write_val port |
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| 152 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
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| 153 | { |
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| 154 | if ((WRITE_ACK [num_port].read() == 1) and |
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| 155 | (WRITE_VAL [num_port].read() == 1)) |
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| 156 | { |
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| 157 | WRITE_VAL [num_port] .write(0); |
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| 158 | nb_ack ++; |
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| 159 | } |
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| 160 | } |
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| 161 | |
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| 162 | SC_START(0); |
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| 163 | } |
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| 164 | |
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| 165 | |
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[58] | 166 | { |
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| 167 | cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl; |
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| 168 | |
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| 169 | nb_val = 0; |
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| 170 | nb_ack = 0; |
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| 171 | Tdata_t read_address [_param->_nb_port_read]; |
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| 172 | |
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| 173 | while (nb_ack < nb_request) |
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| 174 | { |
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| 175 | cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; |
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| 176 | |
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| 177 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
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| 178 | { |
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| 179 | if ((nb_val < nb_request) and |
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| 180 | (READ_VAL [num_port].read() == 0)) |
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| 181 | { |
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| 182 | read_address [num_port] = tab_address[nb_val]; |
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| 183 | READ_VAL [num_port].write(1); |
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| 184 | READ_ADDRESS [num_port].write(read_address [num_port]); |
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| 185 | |
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| 186 | nb_val ++; |
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| 187 | |
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| 188 | if (nb_val >= nb_request) |
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| 189 | break; |
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| 190 | } |
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| 191 | } |
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[53] | 192 | |
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[58] | 193 | SC_START(1); |
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| 194 | |
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| 195 | // reset write_val port |
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| 196 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
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| 197 | { |
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| 198 | if ((READ_ACK [num_port].read() == 1) and |
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| 199 | (READ_VAL [num_port].read() == 1)) |
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| 200 | { |
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| 201 | READ_VAL [num_port] .write(0); |
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| 202 | |
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| 203 | cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl; |
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| 204 | |
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| 205 | TEST(Tdata_t,READ_DATA [num_port].read(), tab_data[read_address [num_port]]); |
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| 206 | nb_ack ++; |
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| 207 | } |
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| 208 | } |
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| 209 | |
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| 210 | SC_START(0); |
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| 211 | } |
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| 212 | } |
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[53] | 213 | } |
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| 214 | |
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| 215 | /******************************************************** |
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| 216 | * Simulation - End |
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| 217 | ********************************************************/ |
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| 218 | |
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| 219 | TEST_OK("End of Simulation"); |
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| 220 | delete _time; |
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| 221 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
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| 222 | |
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| 223 | delete CLOCK; |
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| 224 | delete NRESET; |
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| 225 | #endif |
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| 226 | |
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| 227 | delete _RegisterFile_Multi_Banked; |
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| 228 | } |
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