[53] | 1 | #ifdef SYSTEMC |
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| 2 | /* |
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| 3 | * $Id: RegisterFile_Multi_Banked_allocation.cpp 81 2008-04-15 18:40:01Z rosiere $ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace generic { |
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| 14 | namespace registerfile { |
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| 15 | namespace registerfile_multi_banked { |
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| 16 | |
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| 17 | |
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| 18 | void RegisterFile_Multi_Banked::allocation (void) |
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| 19 | { |
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| 20 | log_printf(FUNC,RegisterFile_Multi_Banked,"allocation","Begin"); |
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| 21 | |
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| 22 | _component = new Component (); |
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| 23 | |
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| 24 | Entity * entity = _component->set_entity (_name |
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| 25 | ,"RegisterFile_Multi_Banked" |
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| 26 | #ifdef POSITION |
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[75] | 27 | ,REGISTER |
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[53] | 28 | #endif |
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| 29 | ); |
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| 30 | |
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| 31 | _interfaces = entity->set_interfaces(); |
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| 32 | |
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| 33 | // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 34 | |
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| 35 | Interface * interface = _interfaces->set_interface("" |
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| 36 | #ifdef POSITION |
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| 37 | ,IN |
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| 38 | ,SOUTH, |
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| 39 | "Generalist interface" |
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| 40 | #endif |
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| 41 | ); |
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| 42 | |
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| 43 | in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES); |
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| 44 | in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); |
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| 45 | |
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| 46 | // ~~~~~[ Interface : "read" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 47 | |
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[57] | 48 | in_READ_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_read]; |
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| 49 | out_READ_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_read]; |
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[62] | 50 | if (_param->_have_port_address == true) |
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[57] | 51 | in_READ_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_read]; |
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| 52 | out_READ_DATA = new SC_OUT(Tdata_t ) * [_param->_nb_port_read]; |
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[53] | 53 | |
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[57] | 54 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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[53] | 55 | { |
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| 56 | Interface_fifo * interface = _interfaces->set_interface("read_"+toString(i) |
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| 57 | #ifdef POSITION |
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| 58 | , IN |
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| 59 | ,WEST |
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| 60 | , "Interface Read" |
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| 61 | #endif |
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| 62 | ); |
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| 63 | |
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| 64 | in_READ_VAL [i] = interface->set_signal_valack_in ("val" , VAL); |
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| 65 | out_READ_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); |
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[62] | 66 | if (_param->_have_port_address == true) |
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[57] | 67 | in_READ_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param->_nb_word))); |
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| 68 | out_READ_DATA [i] = interface->set_signal_out <Tdata_t > ("data" , _param->_size_word); |
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[53] | 69 | } |
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| 70 | |
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| 71 | // ~~~~~[ Interface : "write" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 72 | |
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[57] | 73 | in_WRITE_VAL = new SC_IN (Tcontrol_t) * [_param->_nb_port_write]; |
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| 74 | out_WRITE_ACK = new SC_OUT(Tcontrol_t) * [_param->_nb_port_write]; |
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[62] | 75 | if (_param->_have_port_address == true) |
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[57] | 76 | in_WRITE_ADDRESS = new SC_IN (Taddress_t) * [_param->_nb_port_write]; |
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| 77 | in_WRITE_DATA = new SC_IN (Tdata_t ) * [_param->_nb_port_write]; |
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[53] | 78 | |
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[57] | 79 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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[53] | 80 | { |
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| 81 | Interface_fifo * interface = _interfaces->set_interface("write_"+toString(i) |
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| 82 | #ifdef POSITION |
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| 83 | , IN |
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| 84 | ,EAST |
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| 85 | , "Interface Write" |
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| 86 | #endif |
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| 87 | ); |
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| 88 | |
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| 89 | in_WRITE_VAL [i] = interface->set_signal_valack_in ("val" , VAL); |
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| 90 | out_WRITE_ACK [i] = interface->set_signal_valack_out ("ack" , ACK); |
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[62] | 91 | if (_param->_have_port_address == true) |
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[57] | 92 | in_WRITE_ADDRESS [i] = interface->set_signal_in <Taddress_t> ("address", static_cast<uint32_t>(log2(_param->_nb_word))); |
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| 93 | in_WRITE_DATA [i] = interface->set_signal_in <Tdata_t > ("data" , _param->_size_word); |
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[53] | 94 | } |
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| 95 | |
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| 96 | // ~~~~~[ Registers ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 97 | |
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[78] | 98 | reg_DATA = new Tdata_t * [_param->_nb_bank]; |
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[53] | 99 | |
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[57] | 100 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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[53] | 101 | { |
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[78] | 102 | reg_DATA [i] = new Tdata_t [_param->_nb_word]; |
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[53] | 103 | } |
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| 104 | |
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| 105 | // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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[57] | 106 | internal_WRITE_VAL = new bool [_param->_nb_port_write]; |
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| 107 | internal_WRITE_BANK = new Taddress_t [_param->_nb_port_write]; |
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| 108 | internal_WRITE_NUM_REG = new Taddress_t [_param->_nb_port_write]; |
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[53] | 109 | |
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| 110 | // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 111 | |
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| 112 | #ifdef POSITION |
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| 113 | _component->generate_file(); |
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| 114 | #endif |
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| 115 | |
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| 116 | log_printf(FUNC,RegisterFile_Multi_Banked,"allocation","End"); |
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| 117 | }; |
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| 118 | |
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| 119 | }; // end namespace registerfile_multi_banked |
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| 120 | }; // end namespace registerfile |
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| 121 | }; // end namespace generic |
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| 122 | |
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| 123 | }; // end namespace behavioural |
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| 124 | }; // end namespace morpheo |
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| 125 | #endif |
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