1 | #ifdef VHDL |
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2 | /* |
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3 | * $Id: RegisterFile_Multi_Banked_vhdl_body.cpp 81 2008-04-15 18:40:01Z rosiere $ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace generic { |
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14 | namespace registerfile { |
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15 | namespace registerfile_multi_banked { |
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16 | |
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17 | |
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18 | void RegisterFile_Multi_Banked::vhdl_body (Vhdl * & vhdl) |
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19 | { |
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20 | log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_body","Begin"); |
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21 | |
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22 | uint32_t read_select_limit ; |
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23 | uint32_t read_nb_select1 ; |
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24 | uint32_t read_nb_select2 ; |
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25 | uint32_t write_select_limit; |
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26 | uint32_t write_nb_select1 ; |
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27 | uint32_t write_nb_select2 ; |
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28 | |
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29 | read_select_limit = _param->_nb_port_read%_param->_nb_port_read_by_bank; |
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30 | read_nb_select2 = _param->_nb_port_read/_param->_nb_port_read_by_bank; |
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31 | read_nb_select1 = (read_select_limit==0)?0:(read_nb_select2+1); |
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32 | |
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33 | write_select_limit= _param->_nb_port_write%_param->_nb_port_write_by_bank; |
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34 | write_nb_select2 = _param->_nb_port_write/_param->_nb_port_write_by_bank; |
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35 | write_nb_select1 = (write_select_limit==0)?0:(write_nb_select2+1); |
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36 | |
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37 | vhdl->set_body(""); |
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38 | vhdl->set_body("-----------------------------------"); |
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39 | vhdl->set_body("-- Instance bank "); |
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40 | vhdl->set_body("-----------------------------------"); |
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41 | vhdl->set_body(""); |
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42 | |
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43 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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44 | { |
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45 | vhdl->set_body(_name+"_bank_"+toString(i)+" : "+_name+"_bank"); |
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46 | vhdl->set_body("port map ("); |
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47 | vhdl->set_body("\t in_CLOCK \t=>\tin_CLOCK "); |
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48 | vhdl->set_body("\t, in_NRESET\t=>\tin_NRESET"); |
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49 | for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) |
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50 | { |
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51 | vhdl->set_body("\t, in_READ_"+toString(j)+"_VAL \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_VAL"); |
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52 | vhdl->set_body("\t,out_READ_"+toString(j)+"_ACK \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ACK"); |
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53 | if (_param->_have_bank_port_address == true) |
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54 | vhdl->set_body("\t, in_READ_"+toString(j)+"_ADDRESS \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ADDRESS"); |
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55 | vhdl->set_body("\t,out_READ_"+toString(j)+"_DATA \t=>\tinternal_BANK_READ_"+toString(i)+"_"+toString(j)+"_DATA"); |
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56 | } |
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57 | for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) |
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58 | { |
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59 | vhdl->set_body("\t, in_WRITE_"+toString(j)+"_VAL \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_VAL"); |
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60 | vhdl->set_body("\t,out_WRITE_"+toString(j)+"_ACK \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ACK"); |
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61 | if (_param->_have_bank_port_address == true) |
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62 | vhdl->set_body("\t, in_WRITE_"+toString(j)+"_ADDRESS \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ADDRESS"); |
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63 | vhdl->set_body("\t, in_WRITE_"+toString(j)+"_DATA \t=>\tinternal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_DATA"); |
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64 | } |
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65 | |
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66 | vhdl->set_body(");"); |
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67 | vhdl->set_body(""); |
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68 | } |
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69 | |
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70 | vhdl->set_body(""); |
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71 | vhdl->set_body("-----------------------------------"); |
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72 | vhdl->set_body("-- Instance select"); |
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73 | vhdl->set_body("-- (1 select by port)"); |
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74 | vhdl->set_body("-----------------------------------"); |
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75 | vhdl->set_body(""); |
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76 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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77 | { |
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78 | for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) |
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79 | { |
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80 | uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_read:((j<read_select_limit)?read_nb_select1:read_nb_select2); |
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81 | |
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82 | vhdl->set_body(_name+"_read_select_"+toString(i)+"_"+toString(j)+" : "+_name+"_select_"+toString(nb_port)+"_ports"); |
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83 | vhdl->set_body("port map ("); |
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84 | for (uint32_t k=0; k<nb_port; k++) |
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85 | { |
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86 | uint32_t num_port = (_param->_crossbar == FULL_CROSSBAR)?k:(_param->_nb_port_read_by_bank*k+j); |
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87 | std::string separator = ((k==0)?" ":","); |
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88 | std::string index = (_param->_crossbar == FULL_CROSSBAR)?("_"+toString(j)):""; |
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89 | |
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90 | vhdl->set_body("\t"+separator+" in_VAL_"+toString(k)+" \t=>\tinternal_READ_"+toString(i)+"_"+toString(num_port)+index+"_VAL"); |
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91 | vhdl->set_body("\t,out_ACK_"+toString(k)+" \t=>\tinternal_SELECT_READ_"+toString(i)+"_"+toString(num_port)+index+"_VAL"); |
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92 | } |
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93 | vhdl->set_body(");"); |
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94 | vhdl->set_body(""); |
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95 | } |
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96 | |
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97 | for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) |
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98 | { |
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99 | uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((j<write_select_limit)?write_nb_select1:write_nb_select2); |
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100 | |
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101 | vhdl->set_body(_name+"_write_select_"+toString(i)+"_"+toString(j)+" : "+_name+"_select_"+toString(nb_port)+"_ports"); |
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102 | vhdl->set_body("port map ("); |
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103 | for (uint32_t k=0; k<nb_port; k++) |
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104 | { |
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105 | uint32_t num_port = (_param->_crossbar == FULL_CROSSBAR)?k:(_param->_nb_port_write_by_bank*k+j); |
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106 | std::string separator = ((k==0)?" ":","); |
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107 | std::string index = (_param->_crossbar == FULL_CROSSBAR)?("_"+toString(j)):""; |
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108 | |
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109 | vhdl->set_body("\t"+separator+" in_VAL_"+toString(k)+" \t=>\tinternal_WRITE_"+toString(i)+"_"+toString(num_port)+index+"_VAL"); |
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110 | vhdl->set_body("\t,out_ACK_"+toString(k)+" \t=>\tinternal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+index+"_VAL"); |
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111 | } |
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112 | vhdl->set_body(");"); |
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113 | vhdl->set_body(""); |
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114 | } |
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115 | } |
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116 | |
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117 | vhdl->set_body(""); |
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118 | vhdl->set_body("-----------------------------------"); |
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119 | vhdl->set_body("-- Bank Val"); |
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120 | vhdl->set_body("-----------------------------------"); |
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121 | vhdl->set_body(""); |
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122 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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123 | { |
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124 | for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) |
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125 | { |
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126 | uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_read:((j<read_select_limit)?read_nb_select1:read_nb_select2); |
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127 | |
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128 | vhdl->set_body("internal_BANK_READ_"+toString(i)+"_"+toString(j)+ "_VAL <= '0'"); |
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129 | for (uint32_t k=0; k<nb_port; k++) |
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130 | { |
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131 | uint32_t num_port = (_param->_crossbar == FULL_CROSSBAR)?k:(_param->_nb_port_read_by_bank*k+j); |
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132 | std::string index = (_param->_crossbar == FULL_CROSSBAR)?("_"+toString(j)):""; |
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133 | vhdl->set_body("\tor internal_SELECT_READ_"+toString(i)+"_"+toString(num_port)+index+"_VAL"); |
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134 | } |
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135 | vhdl->set_body(";"); |
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136 | } |
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137 | for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) |
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138 | { |
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139 | uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((j<write_select_limit)?write_nb_select1:write_nb_select2); |
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140 | |
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141 | vhdl->set_body("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+ "_VAL <= '0'"); |
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142 | for (uint32_t k=0; k<nb_port; k++) |
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143 | { |
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144 | uint32_t num_port = (_param->_crossbar == FULL_CROSSBAR)?k:(_param->_nb_port_write_by_bank*k+j); |
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145 | std::string index = (_param->_crossbar == FULL_CROSSBAR)?("_"+toString(j)):""; |
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146 | |
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147 | vhdl->set_body("\tor internal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+index+"_VAL"); |
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148 | } |
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149 | vhdl->set_body(";"); |
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150 | } |
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151 | } |
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152 | |
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153 | vhdl->set_body(""); |
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154 | vhdl->set_body("-----------------------------------"); |
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155 | vhdl->set_body("-- Bank Address"); |
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156 | vhdl->set_body("-----------------------------------"); |
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157 | vhdl->set_body(""); |
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158 | |
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159 | if (_param->_have_bank_port_address == true) |
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160 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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161 | { |
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162 | for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j++) |
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163 | { |
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164 | uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_read:((j<read_select_limit)?read_nb_select1:read_nb_select2); |
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165 | |
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166 | vhdl->set_body("internal_BANK_READ_"+toString(i)+"_"+toString(j)+ "_ADDRESS <="); |
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167 | for (uint32_t k=1; k<nb_port; k++) |
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168 | { |
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169 | uint32_t num_port = (_param->_crossbar == FULL_CROSSBAR)?k:(_param->_nb_port_read_by_bank*k+j); |
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170 | std::string index = (_param->_crossbar == FULL_CROSSBAR)?("_"+toString(j)):""; |
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171 | |
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172 | vhdl->set_body("\tin_READ_"+toString(num_port)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+" when internal_SELECT_READ_"+toString(i)+"_"+toString(num_port)+index+"_VAL ='1' else"); |
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173 | } |
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174 | vhdl->set_body("\tin_READ_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+";"); |
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175 | // vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); |
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176 | } |
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177 | for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) |
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178 | { |
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179 | uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((j<write_select_limit)?write_nb_select1:write_nb_select2); |
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180 | |
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181 | vhdl->set_body("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+ "_ADDRESS <="); |
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182 | for (uint32_t k=1; k<nb_port; k++) |
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183 | { |
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184 | uint32_t num_port = (_param->_crossbar == FULL_CROSSBAR)?k:(_param->_nb_port_write_by_bank*k+j); |
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185 | std::string index = (_param->_crossbar == FULL_CROSSBAR)?("_"+toString(j)):""; |
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186 | |
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187 | vhdl->set_body("\tin_WRITE_"+toString(num_port)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+" when internal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+index+"_VAL='1' else"); |
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188 | } |
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189 | vhdl->set_body("\tin_WRITE_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address_by_bank)+";"); |
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190 | // vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); |
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191 | } |
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192 | } |
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193 | |
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194 | vhdl->set_body(""); |
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195 | vhdl->set_body("-----------------------------------"); |
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196 | vhdl->set_body("-- Bank Data"); |
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197 | vhdl->set_body("-----------------------------------"); |
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198 | vhdl->set_body(""); |
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199 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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200 | { |
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201 | for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++) |
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202 | { |
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203 | uint32_t nb_port = (_param->_crossbar == FULL_CROSSBAR)?_param->_nb_port_write:((j<write_select_limit)?write_nb_select1:write_nb_select2); |
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204 | |
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205 | vhdl->set_body("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+ "_DATA <="); |
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206 | for (uint32_t k=1; k<nb_port; k++) |
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207 | { |
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208 | uint32_t num_port = (_param->_crossbar == FULL_CROSSBAR)?k:(_param->_nb_port_write_by_bank*k+j); |
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209 | std::string index = (_param->_crossbar == FULL_CROSSBAR)?("_"+toString(j)):""; |
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210 | vhdl->set_body("\tin_WRITE_"+toString(num_port)+"_DATA when internal_SELECT_WRITE_"+toString(i)+"_"+toString(num_port)+index+"_VAL='1' else"); |
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211 | } |
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212 | vhdl->set_body("\tin_WRITE_"+toString(j)+"_DATA;"); |
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213 | // vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); |
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214 | } |
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215 | } |
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216 | |
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217 | vhdl->set_body(""); |
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218 | vhdl->set_body("-----------------------------------"); |
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219 | vhdl->set_body("-- VAL (to Select)"); |
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220 | vhdl->set_body("-----------------------------------"); |
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221 | vhdl->set_body(""); |
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222 | |
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223 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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224 | { |
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225 | for (uint32_t j=0; j<_param->_nb_port_read; j ++) |
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226 | { |
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227 | std::string str_address; |
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228 | |
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229 | if (_param->_have_bank_port_address == true) |
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230 | str_address = (_param->_nb_bank==1)?"":("and (in_READ_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address-1,_param->_size_address_by_bank)+"="+std_logic_conv( _param->_size_address-_param->_size_address_by_bank,i)+") "); |
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231 | else |
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232 | str_address = ""; |
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233 | |
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234 | vhdl->set_body("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL <= '1' when (in_READ_"+toString(j)+"_VAL ='1') "+str_address+"else '0';"); |
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235 | } |
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236 | for (uint32_t j=0; j<_param->_nb_port_write; j ++) |
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237 | { |
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238 | std::string str_address; |
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239 | |
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240 | if (_param->_have_port_address == true) |
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241 | str_address = (_param->_nb_bank==1)?"":("and (in_WRITE_"+toString(j)+"_ADDRESS"+std_logic_range(_param->_size_address-1,_param->_size_address_by_bank)+"="+std_logic_conv( _param->_size_address-_param->_size_address_by_bank,i)+") "); |
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242 | else |
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243 | str_address = ""; |
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244 | |
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245 | vhdl->set_body("internal_WRITE_"+toString(i)+"_"+toString(j)+"_VAL <= '1' when (in_WRITE_"+toString(j)+"_VAL='1') "+str_address+"else '0';"); |
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246 | } |
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247 | } |
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248 | |
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249 | if (_param->_crossbar == FULL_CROSSBAR) |
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250 | { |
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251 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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252 | { |
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253 | for (uint32_t j=0; j<_param->_nb_port_read; j++) |
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254 | { |
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255 | for (uint32_t k=0; k<_param->_nb_port_read_by_bank; k++) |
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256 | { |
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257 | vhdl->set_body("internal_READ_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL <= internal_READ_"+toString(i)+"_"+toString(j)+"_VAL and not"); |
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258 | vhdl->set_body("\t('0'"); |
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259 | for (uint32_t l=0; l<k; l++) |
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260 | { |
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261 | vhdl->set_body("\tor internal_SELECT_READ_"+toString(i)+"_"+toString(j)+"_"+toString(l)+"_VAL"); |
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262 | } |
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263 | |
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264 | vhdl->set_body("\t);"); |
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265 | } |
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266 | } |
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267 | for (uint32_t j=0; j<_param->_nb_port_write; j++) |
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268 | { |
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269 | for (uint32_t k=0; k<_param->_nb_port_write_by_bank; k++) |
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270 | { |
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271 | vhdl->set_body("internal_WRITE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL <= internal_WRITE_"+toString(i)+"_"+toString(j)+"_VAL and not"); |
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272 | vhdl->set_body("\t('0'"); |
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273 | |
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274 | for (uint32_t l=0; l<k; l++) |
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275 | { |
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276 | vhdl->set_body("\tor internal_SELECT_WRITE_"+toString(i)+"_"+toString(j)+"_"+toString(l)+"_VAL"); |
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277 | } |
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278 | |
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279 | vhdl->set_body("\t);"); |
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280 | } |
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281 | } |
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282 | } |
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283 | } |
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284 | vhdl->set_body(""); |
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285 | vhdl->set_body("-----------------------------------"); |
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286 | vhdl->set_body("-- OUTPUT"); |
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287 | vhdl->set_body("-----------------------------------"); |
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288 | vhdl->set_body(""); |
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289 | |
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290 | if (_param->_crossbar == FULL_CROSSBAR) |
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291 | { |
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292 | for (uint32_t i=0; i<_param->_nb_port_read; i ++) |
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293 | { |
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294 | vhdl->set_body("out_READ_"+toString(i)+"_ACK <= "); |
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295 | for (uint32_t j=0; j<_param->_nb_bank; j ++) |
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296 | { |
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297 | for (uint32_t k=0; k<_param->_nb_port_read_by_bank; k ++) |
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298 | { |
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299 | vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(k)+"_ACK when internal_SELECT_READ_"+toString(j)+"_"+toString(i)+"_"+toString(k)+"_VAL = '1' else"); |
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300 | } |
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301 | } |
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302 | vhdl->set_body("\t'0';"); |
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303 | vhdl->set_body("out_READ_"+toString(i)+"_DATA <= "); |
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304 | for (uint32_t j=0; j<_param->_nb_bank; j ++) |
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305 | { |
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306 | for (uint32_t k=0; k<_param->_nb_port_read_by_bank; k ++) |
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307 | { |
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308 | vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(k)+"_DATA when internal_SELECT_READ_"+toString(j)+"_"+toString(i)+"_"+toString(k)+"_VAL = '1' else"); |
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309 | } |
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310 | } |
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311 | vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); |
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312 | } |
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313 | for (uint32_t i=0; i<_param->_nb_port_write; i ++) |
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314 | { |
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315 | vhdl->set_body("out_WRITE_"+toString(i)+"_ACK <= "); |
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316 | for (uint32_t j=0; j<_param->_nb_bank; j ++) |
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317 | { |
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318 | for (uint32_t k=0; k<_param->_nb_port_write_by_bank; k ++) |
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319 | { |
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320 | vhdl->set_body("\tinternal_BANK_WRITE_"+toString(j)+"_"+toString(k)+"_ACK when internal_SELECT_WRITE_"+toString(j)+"_"+toString(i)+"_"+toString(k)+"_VAL = '1' else"); |
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321 | } |
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322 | } |
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323 | vhdl->set_body("\t'0';"); |
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324 | } |
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325 | } |
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326 | else |
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327 | { |
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328 | for (uint32_t i=0; i<_param->_nb_port_read; i ++) |
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329 | { |
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330 | uint32_t link = _param->_link_port_read_to_bank_read[i]; |
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331 | |
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332 | vhdl->set_body("out_READ_"+toString(i)+"_ACK <= "); |
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333 | for (uint32_t j=0; j<_param->_nb_bank; j ++) |
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334 | { |
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335 | vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(link)+"_ACK when internal_SELECT_READ_"+toString(j)+"_"+toString(i)+"_VAL = '1' else"); |
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336 | } |
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337 | // vhdl->set_body("\tinternal_BANK_READ_"+toString(0)+"_"+toString(link)+"_ACK;"); |
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338 | vhdl->set_body("\t'0';"); |
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339 | |
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340 | vhdl->set_body("out_READ_"+toString(i)+"_DATA <= "); |
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341 | for (uint32_t j=1; j<_param->_nb_bank; j ++) |
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342 | { |
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343 | vhdl->set_body("\tinternal_BANK_READ_"+toString(j)+"_"+toString(link)+"_DATA when internal_SELECT_READ_"+toString(j)+"_"+toString(i)+"_VAL = '1' else"); |
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344 | } |
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345 | vhdl->set_body("\tinternal_BANK_READ_"+toString(0)+"_"+toString(link)+"_DATA;"); |
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346 | // vhdl->set_body("\t"+std_logic_others(_param->_size_word,0)+";"); |
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347 | } |
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348 | for (uint32_t i=0; i<_param->_nb_port_write; i ++) |
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349 | { |
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350 | uint32_t link = _param->_link_port_write_to_bank_write[i]; |
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351 | |
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352 | vhdl->set_body("out_WRITE_"+toString(i)+"_ACK <= "); |
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353 | for (uint32_t j=0; j<_param->_nb_bank; j ++) |
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354 | { |
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355 | vhdl->set_body("\tinternal_BANK_WRITE_"+toString(j)+"_"+toString(link)+"_ACK when internal_SELECT_WRITE_"+toString(j)+"_"+toString(i)+"_VAL = '1' else"); |
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356 | } |
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357 | // vhdl->set_body("\tinternal_BANK_WRITE_"+toString(0)+"_"+toString(link)+"_ACK;"); |
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358 | vhdl->set_body("\t'0';"); |
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359 | } |
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360 | } |
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361 | |
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362 | log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_body","End"); |
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363 | }; |
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364 | |
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365 | }; // end namespace registerfile_multi_banked |
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366 | }; // end namespace registerfile |
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367 | }; // end namespace generic |
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368 | }; // end namespace behavioural |
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369 | }; // end namespace morpheo |
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370 | #endif |
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