1 | #ifdef VHDL |
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2 | /* |
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3 | * $Id$ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace generic { |
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14 | namespace registerfile { |
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15 | namespace registerfile_multi_banked { |
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16 | |
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17 | |
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18 | void RegisterFile_Multi_Banked::vhdl_declaration (Vhdl * & vhdl) |
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19 | { |
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20 | log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_declaration","Begin"); |
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21 | |
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22 | for (uint32_t i=0; i<_param->_nb_bank; i++) |
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23 | { |
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24 | for (uint32_t j=0; j<_param->_nb_port_read; j ++) |
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25 | { |
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26 | if (_param->_crossbar == FULL_CROSSBAR) |
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27 | { |
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28 | for (uint32_t k=0; k<_param->_nb_port_read_by_bank; k++) |
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29 | { |
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30 | vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL" ,1); |
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31 | vhdl->set_signal ("internal_SELECT_READ_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL" ,1); |
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32 | } |
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33 | } |
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34 | else |
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35 | vhdl->set_signal ("internal_SELECT_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1); |
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36 | vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1); |
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37 | vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_ACK" ,1); |
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38 | } |
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39 | for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j ++) |
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40 | { |
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41 | vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1); |
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42 | vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ACK" ,1); |
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43 | if (_param->_have_bank_port_address == true) |
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44 | vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ADDRESS",_param->_size_address_by_bank); |
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45 | vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_DATA" ,_param->_size_word); |
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46 | } |
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47 | |
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48 | for (uint32_t j=0; j<_param->_nb_port_write; j ++) |
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49 | { |
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50 | if (_param->_crossbar == FULL_CROSSBAR) |
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51 | { |
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52 | for (uint32_t k=0; k<_param->_nb_port_write_by_bank; k++) |
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53 | { |
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54 | vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL" ,1); |
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55 | vhdl->set_signal ("internal_SELECT_WRITE_"+toString(i)+"_"+toString(j)+"_"+toString(k)+"_VAL" ,1); |
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56 | } |
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57 | } |
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58 | else |
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59 | vhdl->set_signal ("internal_SELECT_WRITE_"+toString(i)+"_"+toString(j)+"_VAL" ,1); |
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60 | vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_VAL" ,1); |
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61 | vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_ACK" ,1); |
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62 | } |
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63 | for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j ++) |
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64 | { |
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65 | vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_VAL" ,1); |
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66 | vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ACK" ,1); |
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67 | if (_param->_have_bank_port_address == true) |
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68 | vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ADDRESS",_param->_size_address_by_bank); |
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69 | vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_DATA" ,_param->_size_word); |
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70 | } |
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71 | } |
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72 | |
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73 | log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_declaration","End"); |
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74 | }; |
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75 | |
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76 | }; // end namespace registerfile_multi_banked |
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77 | }; // end namespace registerfile |
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78 | }; // end namespace generic |
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79 | |
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80 | }; // end namespace behavioural |
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81 | }; // end namespace morpheo |
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82 | #endif |
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