1 | #ifdef VHDL |
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2 | /* |
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3 | * $Id$ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace generic { |
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14 | namespace registerfile { |
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15 | namespace registerfile_multi_banked { |
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16 | |
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17 | |
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18 | void RegisterFile_Multi_Banked::vhdl_declaration (Vhdl * & vhdl) |
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19 | { |
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20 | log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_declaration","Begin"); |
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21 | |
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22 | vhdl->set_type ("Tregfile", "array (" + toString(_param._nb_word_by_bank-1) + " downto 0) of " + std_logic(_param._size_word)); |
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23 | |
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24 | vhdl->set_type ("Tbank" , "array (" + toString(_param._nb_bank) + " downto 0) of Tregfile"); |
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25 | |
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26 | vhdl->set_signal ("reg_DATA", "Tbank"); |
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27 | |
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28 | for (uint32_t i=0; i<_param._nb_bank; i++) |
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29 | { |
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30 | for (uint32_t j=0; j<_param._nb_port_read_by_bank; j ++) |
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31 | { |
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32 | vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1); |
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33 | vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_PORT" ,static_cast<uint32_t>(ceil(log2(_param._nb_port_read)))); |
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34 | } |
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35 | for (uint32_t j=0; j<_param._nb_port_write_by_bank; j ++) |
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36 | { |
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37 | vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_VAL" ,1); |
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38 | vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_PORT",static_cast<uint32_t>(ceil(log2(_param._nb_port_write)))); |
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39 | } |
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40 | } |
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41 | |
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42 | log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_declaration","End"); |
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43 | }; |
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44 | |
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45 | }; // end namespace registerfile_multi_banked |
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46 | }; // end namespace registerfile |
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47 | }; // end namespace generic |
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48 | |
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49 | }; // end namespace behavioural |
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50 | }; // end namespace morpheo |
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51 | #endif |
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