[10] | 1 | #ifdef VHDL_TESTBENCH |
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| 2 | /* |
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| 3 | * $Id$ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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[15] | 9 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/include/RegisterFile_Multi_Banked.h" |
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[10] | 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace generic { |
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[15] | 14 | namespace registerfile{ |
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[10] | 15 | namespace registerfile_multi_banked { |
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| 16 | |
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| 17 | |
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| 18 | void RegisterFile_Multi_Banked::vhdl_testbench_transition () |
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| 19 | { |
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| 20 | log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_testbench_transition","Begin"); |
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| 21 | |
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| 22 | // Evaluation before read the ouput signal |
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| 23 | sc_start(0); |
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| 24 | |
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| 25 | // In order with file RegisterFile_Multi_Banked_vhdl_testbench_port.cpp |
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| 26 | // Warning : if a output depend of a subcomponent, take directly the port of subcomponent |
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| 27 | // (because we have no control on the ordonnancer's policy) |
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| 28 | |
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| 29 | _vhdl_testbench->add_input (PORT_READ( in_NRESET)); |
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| 30 | |
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| 31 | // ----- Interface Read |
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| 32 | for (uint32_t i=0; i<_param._nb_port_read; i++) |
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| 33 | { |
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| 34 | _vhdl_testbench->add_input (PORT_READ( in_READ_VAL [i])); |
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| 35 | _vhdl_testbench->add_output(PORT_READ( out_READ_ACK [i])); |
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| 36 | _vhdl_testbench->add_input (PORT_READ( in_READ_ADDRESS [i])); |
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| 37 | _vhdl_testbench->add_output(PORT_READ( out_READ_DATA [i])); |
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| 38 | } |
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| 39 | |
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| 40 | // ----- Interface Write |
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| 41 | for (uint32_t i=0; i<_param._nb_port_write; i++) |
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| 42 | { |
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| 43 | _vhdl_testbench->add_input (PORT_READ( in_WRITE_VAL [i])); |
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| 44 | _vhdl_testbench->add_output(PORT_READ( out_WRITE_ACK [i])); |
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| 45 | _vhdl_testbench->add_input (PORT_READ( in_WRITE_ADDRESS [i])); |
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| 46 | _vhdl_testbench->add_input (PORT_READ( in_WRITE_DATA [i])); |
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| 47 | } |
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| 48 | |
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| 49 | |
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| 50 | // add_test : |
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| 51 | // - True : the cycle must be compare with the output of systemC |
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| 52 | // - False : no test |
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| 53 | _vhdl_testbench->add_test(true); |
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| 54 | |
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| 55 | _vhdl_testbench->new_cycle (); // always at the end |
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| 56 | |
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| 57 | log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_testbench_transition","End"); |
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| 58 | }; |
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| 59 | |
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| 60 | }; // end namespace registerfile_multi_banked |
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[15] | 61 | }; // end namespace registerfile |
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[10] | 62 | }; // end namespace generic |
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| 63 | |
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| 64 | }; // end namespace behavioural |
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| 65 | }; // end namespace morpheo |
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| 66 | #endif |
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