[53] | 1 | /* |
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| 2 | * $Id: test.cpp 113 2009-04-14 18:39:12Z rosiere $ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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| 9 | #define NB_ITERATION 1 |
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| 10 | #define CYCLE_MAX (256*NB_ITERATION) |
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| 11 | |
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[82] | 12 | #include "Behavioural/Generic/RegisterFile/SelfTest/include/test.h" |
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| 13 | #include "Common/include/Test.h" |
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[53] | 14 | |
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| 15 | void test (string name, |
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| 16 | morpheo::behavioural::generic::registerfile::Parameters * _param) |
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| 17 | { |
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| 18 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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| 19 | |
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| 20 | #ifdef STATISTICS |
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[62] | 21 | morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics(5,50); |
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[53] | 22 | #endif |
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| 23 | |
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[88] | 24 | Tusage_t _usage = USE_ALL; |
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| 25 | |
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| 26 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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| 27 | // _usage = usage_unset(_usage,USE_VHDL ); |
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| 28 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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| 29 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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| 30 | // _usage = usage_unset(_usage,USE_POSITION ); |
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| 31 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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| 32 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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| 33 | |
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[62] | 34 | RegisterFile * _RegisterFile = new RegisterFile (name.c_str(), |
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| 35 | #ifdef STATISTICS |
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| 36 | _param_stat, |
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| 37 | #endif |
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[82] | 38 | _param, |
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[88] | 39 | _usage); |
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[62] | 40 | |
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[53] | 41 | #ifdef SYSTEMC |
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| 42 | /********************************************************************* |
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| 43 | * Déclarations des signaux |
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| 44 | *********************************************************************/ |
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| 45 | sc_clock * CLOCK; |
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| 46 | sc_signal<Tcontrol_t> * NRESET; |
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| 47 | |
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| 48 | sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read]; |
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| 49 | sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read]; |
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[81] | 50 | sc_signal<registerfile::Taddress_t> READ_ADDRESS [_param->_nb_port_read]; |
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[53] | 51 | sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read]; |
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| 52 | |
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| 53 | sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write]; |
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| 54 | sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write]; |
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[81] | 55 | sc_signal<registerfile::Taddress_t> WRITE_ADDRESS [_param->_nb_port_write]; |
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[53] | 56 | sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write]; |
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| 57 | |
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| 58 | string rename; |
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| 59 | |
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| 60 | CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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| 61 | NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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| 62 | |
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| 63 | /******************************************************** |
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| 64 | * Instanciation |
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| 65 | ********************************************************/ |
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| 66 | |
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| 67 | cout << "<" << name << "> Instanciation of _RegisterFile" << endl; |
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| 68 | |
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| 69 | (*(_RegisterFile->in_CLOCK)) (*(CLOCK)); |
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| 70 | (*(_RegisterFile->in_NRESET)) (*(NRESET)); |
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| 71 | |
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| 72 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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| 73 | { |
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| 74 | (*(_RegisterFile-> in_READ_VAL [i])) (READ_VAL [i]); |
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| 75 | (*(_RegisterFile->out_READ_ACK [i])) (READ_ACK [i]); |
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[62] | 76 | if (_param->_have_port_address == true) |
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[53] | 77 | (*(_RegisterFile-> in_READ_ADDRESS [i])) (READ_ADDRESS [i]); |
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| 78 | (*(_RegisterFile->out_READ_DATA [i])) (READ_DATA [i]); |
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| 79 | } |
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| 80 | |
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| 81 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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| 82 | { |
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| 83 | (*(_RegisterFile-> in_WRITE_VAL [i])) (WRITE_VAL [i]); |
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| 84 | (*(_RegisterFile->out_WRITE_ACK [i])) (WRITE_ACK [i]); |
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[62] | 85 | if (_param->_have_port_address == true) |
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[53] | 86 | (*(_RegisterFile-> in_WRITE_ADDRESS [i])) (WRITE_ADDRESS [i]); |
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| 87 | (*(_RegisterFile-> in_WRITE_DATA [i])) (WRITE_DATA [i]); |
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| 88 | } |
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| 89 | |
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| 90 | cout << "<" << name << "> Start Simulation ............" << endl; |
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| 91 | Time * _time = new Time(); |
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| 92 | |
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| 93 | /******************************************************** |
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| 94 | * Simulation - Begin |
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| 95 | ********************************************************/ |
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| 96 | |
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| 97 | const bool simulate_read = true; |
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| 98 | const uint32_t nb_request = _param->_nb_word; |
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| 99 | // random init |
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| 100 | const uint32_t grain = 0; |
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| 101 | //const uint32_t grain = static_cast<uint32_t>(time(NULL)); |
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| 102 | |
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| 103 | srand(grain); |
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| 104 | |
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| 105 | // Initialisation |
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| 106 | |
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| 107 | SC_START(0); |
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| 108 | |
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| 109 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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| 110 | WRITE_VAL [i] .write (0); |
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| 111 | |
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| 112 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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| 113 | READ_VAL [i] .write (0); |
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| 114 | |
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| 115 | NRESET->write(0); |
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| 116 | |
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| 117 | SC_START(5); |
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| 118 | |
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| 119 | NRESET->write(1); |
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| 120 | |
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| 121 | for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++) |
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| 122 | { |
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| 123 | cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl; |
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| 124 | |
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[81] | 125 | registerfile::Taddress_t nb_val = 0; |
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| 126 | registerfile::Taddress_t nb_ack = 0; |
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[53] | 127 | |
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| 128 | Tdata_t tab_data [_param->_nb_word]; |
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[81] | 129 | registerfile::Taddress_t tab_address [nb_request ]; |
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[53] | 130 | |
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| 131 | for (uint32_t i=0; i<_param->_nb_word; i++) |
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| 132 | tab_data [i]= rand()%(1<<(_param->_size_word-1)); |
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| 133 | for (uint32_t i=0; i<nb_request; i++) |
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| 134 | tab_address [i]= rand()%(1<<(_param->_size_address)); |
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| 135 | |
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| 136 | while (nb_ack < nb_request) |
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| 137 | { |
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[113] | 138 | cout << "cycle : " << static_cast<uint32_t> (simulation_cycle()) << endl; |
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[53] | 139 | |
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| 140 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
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| 141 | { |
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| 142 | if ((nb_val < nb_request) and |
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| 143 | (WRITE_VAL [num_port].read() == 0)) |
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| 144 | { |
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| 145 | cout << "(" << num_port << ") [" << tab_address[nb_val] << "] <= " << tab_data[tab_address[nb_val]] << endl; |
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| 146 | |
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| 147 | WRITE_VAL [num_port] .write(1); |
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| 148 | WRITE_DATA [num_port] .write(tab_data[tab_address[nb_val]]); |
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| 149 | WRITE_ADDRESS [num_port] .write(tab_address[nb_val]); |
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| 150 | |
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| 151 | nb_val ++; |
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| 152 | |
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| 153 | // Address can be not a multiple of nb_port_write |
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| 154 | if (nb_val >= nb_request) |
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| 155 | break; |
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| 156 | } |
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| 157 | } |
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| 158 | |
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| 159 | SC_START(1); |
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| 160 | |
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| 161 | // reset write_val port |
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| 162 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
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| 163 | { |
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| 164 | if ((WRITE_ACK [num_port].read() == 1) and |
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| 165 | (WRITE_VAL [num_port].read() == 1)) |
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| 166 | { |
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| 167 | WRITE_VAL [num_port] .write(0); |
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| 168 | nb_ack ++; |
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| 169 | } |
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| 170 | } |
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| 171 | |
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| 172 | SC_START(0); |
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| 173 | } |
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| 174 | |
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| 175 | |
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| 176 | if (simulate_read == true) |
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| 177 | { |
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| 178 | cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl; |
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| 179 | |
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| 180 | nb_val = 0; |
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| 181 | nb_ack = 0; |
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| 182 | Tdata_t read_address [_param->_nb_port_read]; |
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| 183 | |
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| 184 | while (nb_ack < nb_request) |
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| 185 | { |
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[113] | 186 | cout << "cycle : " << static_cast<uint32_t> (simulation_cycle()) << endl; |
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[53] | 187 | |
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| 188 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
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| 189 | { |
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| 190 | if ((nb_val < nb_request) and |
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| 191 | (READ_VAL [num_port].read() == 0)) |
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| 192 | { |
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| 193 | read_address [num_port] = tab_address[nb_val]; |
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| 194 | READ_VAL [num_port].write(1); |
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| 195 | READ_ADDRESS [num_port].write(read_address [num_port]); |
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| 196 | |
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| 197 | nb_val ++; |
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| 198 | |
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| 199 | if (nb_val >= nb_request) |
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| 200 | break; |
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| 201 | } |
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| 202 | } |
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| 203 | |
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| 204 | SC_START(1); |
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| 205 | |
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| 206 | // reset write_val port |
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| 207 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
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| 208 | { |
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| 209 | if ((READ_ACK [num_port].read() == 1) and |
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| 210 | (READ_VAL [num_port].read() == 1)) |
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| 211 | { |
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| 212 | READ_VAL [num_port] .write(0); |
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| 213 | |
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| 214 | cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl; |
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| 215 | |
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| 216 | TEST(Tdata_t,READ_DATA [num_port].read(), tab_data[read_address [num_port]]); |
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| 217 | nb_ack ++; |
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| 218 | } |
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| 219 | } |
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| 220 | |
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| 221 | SC_START(0); |
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| 222 | } |
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| 223 | } |
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| 224 | } |
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| 225 | |
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| 226 | /******************************************************** |
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| 227 | * Simulation - End |
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| 228 | ********************************************************/ |
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| 229 | |
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| 230 | TEST_OK ("End of Simulation"); |
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| 231 | delete _time; |
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| 232 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
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| 233 | |
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| 234 | delete CLOCK; |
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| 235 | delete NRESET; |
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| 236 | #endif |
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| 237 | |
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| 238 | delete _RegisterFile; |
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| 239 | } |
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