[2] | 1 | /* |
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| 2 | * $Id$ |
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| 3 | * |
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| 4 | * [ Description ] |
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| 5 | * |
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| 6 | * Test |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Generic/RegisterFile/SelfTest/include/test.h" |
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| 10 | #include "Include/Test.h" |
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| 11 | |
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| 12 | void test (string name, |
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| 13 | morpheo::behavioural::generic::registerfile::Parameters param) |
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| 14 | { |
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| 15 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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| 16 | |
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| 17 | try |
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| 18 | { |
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| 19 | cout << param.print(1); |
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| 20 | param.test(); |
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| 21 | } |
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| 22 | catch (morpheo::ErrorMorpheo & error) |
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| 23 | { |
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| 24 | cout << "<" << name << "> : " << error.what (); |
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| 25 | return; |
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| 26 | } |
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| 27 | catch (...) |
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| 28 | { |
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| 29 | cerr << "<" << name << "> : This test must generate a error" << endl; |
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| 30 | exit (EXIT_FAILURE); |
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| 31 | } |
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| 32 | |
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| 33 | RegisterFile * registerfile = new RegisterFile (name.c_str(), |
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| 34 | #ifdef STATISTICS |
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| 35 | morpheo::behavioural::Parameters_Statistics(5,50), |
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| 36 | #endif |
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| 37 | param); |
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| 38 | |
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| 39 | #ifdef SYSTEMC |
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| 40 | /********************************************************************* |
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| 41 | * Déclarations des signaux |
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| 42 | *********************************************************************/ |
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| 43 | sc_clock CLOCK ("clock", 1.0, 0.5); |
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| 44 | |
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| 45 | sc_signal<Tcontrol_t> READ_ENABLE [param._nb_port_read]; |
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| 46 | sc_signal<Taddress_t> READ_ADDRESS [param._nb_port_read]; |
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| 47 | sc_signal<Tdata_t> READ_DATA [param._nb_port_read]; |
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| 48 | |
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| 49 | sc_signal<Tcontrol_t> WRITE_ENABLE [param._nb_port_write]; |
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| 50 | sc_signal<Taddress_t> WRITE_ADDRESS [param._nb_port_write]; |
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| 51 | sc_signal<Tdata_t> WRITE_DATA [param._nb_port_write]; |
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| 52 | |
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| 53 | /******************************************************** |
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| 54 | * Instanciation |
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| 55 | ********************************************************/ |
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| 56 | |
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| 57 | cout << "<" << name << "> Instanciation of registerFile" << endl; |
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| 58 | |
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| 59 | (*(registerfile->in_CLOCK)) (CLOCK); |
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| 60 | |
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| 61 | for (uint32_t i=0; i<param._nb_port_read; i++) |
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| 62 | { |
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| 63 | (*(registerfile-> in_READ_ENABLE [i])) (READ_ENABLE [i]); |
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| 64 | (*(registerfile-> in_READ_ADDRESS [i])) (READ_ADDRESS [i]); |
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| 65 | (*(registerfile->out_READ_DATA [i])) (READ_DATA [i]); |
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| 66 | } |
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| 67 | |
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| 68 | for (uint32_t i=0; i<param._nb_port_write; i++) |
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| 69 | { |
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| 70 | (*(registerfile-> in_WRITE_ENABLE [i])) (WRITE_ENABLE [i]); |
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| 71 | (*(registerfile-> in_WRITE_ADDRESS [i])) (WRITE_ADDRESS [i]); |
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| 72 | (*(registerfile-> in_WRITE_DATA [i])) (WRITE_DATA [i]); |
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| 73 | } |
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| 74 | |
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| 75 | /******************************************************** |
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| 76 | * Simulation - Begin |
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| 77 | ********************************************************/ |
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| 78 | |
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| 79 | cout << "<" << name << "> Start Simulation ............" << endl; |
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| 80 | // Initialisation |
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| 81 | |
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| 82 | sc_start(0); |
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| 83 | |
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| 84 | for (uint32_t i=0; i<param._nb_port_write; i++) |
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| 85 | WRITE_ENABLE [i] .write (0); |
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| 86 | |
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| 87 | for (uint32_t i=0; i<param._nb_port_read; i++) |
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| 88 | READ_ENABLE [i] .write (0); |
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| 89 | |
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| 90 | sc_start(5); |
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| 91 | |
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| 92 | cout << "<" << name << "> Write the RegisterFile (no read)" << endl; |
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| 93 | |
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| 94 | uint32_t grain = 0; |
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| 95 | //uint32_t grain = static_cast<uint32_t>(time(NULL)); |
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| 96 | |
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| 97 | srand(grain); |
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| 98 | |
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| 99 | Tdata_t data, data_wait; |
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| 100 | Taddress_t address = 0; |
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| 101 | |
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| 102 | while (address < param._nb_word) |
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| 103 | { |
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| 104 | uint32_t num_port = 0; |
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| 105 | |
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| 106 | cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; |
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| 107 | |
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| 108 | while (num_port<param._nb_port_write) |
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| 109 | { |
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| 110 | data = rand()%(1<<(param._size_word-1)); |
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| 111 | |
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| 112 | cout << "(" << num_port << ") [" << address << "] <= " << data << endl; |
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| 113 | WRITE_ENABLE [num_port] .write(1); |
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| 114 | WRITE_DATA [num_port] .write(data); |
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| 115 | WRITE_ADDRESS [num_port] .write(address); |
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| 116 | |
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| 117 | address ++; |
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| 118 | num_port ++; |
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| 119 | // Address can be not a multiple of nb_port_write |
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| 120 | if (address >= param._nb_word) |
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| 121 | break; |
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| 122 | } |
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| 123 | |
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| 124 | while (num_port<param._nb_port_write) |
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| 125 | { |
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| 126 | WRITE_ENABLE [num_port] .write(0); |
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| 127 | num_port ++; |
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| 128 | } |
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| 129 | |
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| 130 | sc_start(1); |
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| 131 | } |
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| 132 | cout << "<" << name << "> Read the RegisterFile (no write)" << endl; |
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| 133 | |
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| 134 | srand(grain); |
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| 135 | |
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| 136 | for (uint32_t i=0; i<param._nb_port_write; i++) |
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| 137 | WRITE_ENABLE [i] .write (0); |
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| 138 | |
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| 139 | sc_start(1); |
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| 140 | |
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| 141 | address = 0; |
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| 142 | while (address < param._nb_word) |
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| 143 | { |
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| 144 | uint32_t num_port = 0; |
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| 145 | |
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| 146 | cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; |
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| 147 | |
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| 148 | while (num_port<param._nb_port_read) |
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| 149 | { |
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| 150 | READ_ENABLE [num_port] .write(1); |
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| 151 | READ_ADDRESS [num_port] .write(address); |
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| 152 | |
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| 153 | sc_start(0); // evaluation |
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| 154 | |
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| 155 | data_wait = rand()%(1<<(param._size_word-1)); |
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| 156 | data = READ_DATA [num_port] .read(); |
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| 157 | |
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| 158 | cout << "(" << num_port << ") [" << address << "] => " << data << endl; |
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| 159 | |
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| 160 | TEST(Tdata_t,data,data_wait); |
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| 161 | |
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| 162 | address ++; |
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| 163 | num_port ++; |
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| 164 | if (address >= param._nb_word) |
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| 165 | break; |
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| 166 | } |
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| 167 | |
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| 168 | while (num_port<param._nb_port_read) |
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| 169 | { |
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| 170 | READ_ENABLE [num_port] .write(0); |
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| 171 | num_port ++; |
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| 172 | } |
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| 173 | |
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| 174 | sc_start(1); |
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| 175 | } |
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| 176 | |
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| 177 | for (uint32_t i=0; i<param._nb_port_read; i++) |
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| 178 | READ_ENABLE [i] .write (0); |
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| 179 | |
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| 180 | sc_start(1); |
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| 181 | |
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| 182 | /******************************************************** |
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| 183 | * Simulation - End |
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| 184 | ********************************************************/ |
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| 185 | |
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| 186 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
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| 187 | |
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| 188 | #endif |
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| 189 | |
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| 190 | delete registerfile; |
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| 191 | } |
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