1 | /* |
---|
2 | * $Id: test.cpp 88 2008-12-10 18:31:39Z rosiere $ |
---|
3 | * |
---|
4 | * [ Description ] |
---|
5 | * |
---|
6 | * Test |
---|
7 | */ |
---|
8 | |
---|
9 | #define NB_ITERATION 1 |
---|
10 | #define CYCLE_MAX (256*NB_ITERATION) |
---|
11 | |
---|
12 | #include "Behavioural/Generic/RegisterFile/SelfTest/include/test.h" |
---|
13 | #include "Common/include/Test.h" |
---|
14 | |
---|
15 | void test (string name, |
---|
16 | morpheo::behavioural::generic::registerfile::Parameters * _param) |
---|
17 | { |
---|
18 | cout << "<" << name << "> : Simulation SystemC" << endl; |
---|
19 | |
---|
20 | #ifdef STATISTICS |
---|
21 | morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics(5,50); |
---|
22 | #endif |
---|
23 | |
---|
24 | Tusage_t _usage = USE_ALL; |
---|
25 | |
---|
26 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
---|
27 | // _usage = usage_unset(_usage,USE_VHDL ); |
---|
28 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
---|
29 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
---|
30 | // _usage = usage_unset(_usage,USE_POSITION ); |
---|
31 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
---|
32 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
---|
33 | |
---|
34 | RegisterFile * _RegisterFile = new RegisterFile (name.c_str(), |
---|
35 | #ifdef STATISTICS |
---|
36 | _param_stat, |
---|
37 | #endif |
---|
38 | _param, |
---|
39 | _usage); |
---|
40 | |
---|
41 | #ifdef SYSTEMC |
---|
42 | /********************************************************************* |
---|
43 | * Déclarations des signaux |
---|
44 | *********************************************************************/ |
---|
45 | sc_clock * CLOCK; |
---|
46 | sc_signal<Tcontrol_t> * NRESET; |
---|
47 | |
---|
48 | sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read]; |
---|
49 | sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read]; |
---|
50 | sc_signal<registerfile::Taddress_t> READ_ADDRESS [_param->_nb_port_read]; |
---|
51 | sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read]; |
---|
52 | |
---|
53 | sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write]; |
---|
54 | sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write]; |
---|
55 | sc_signal<registerfile::Taddress_t> WRITE_ADDRESS [_param->_nb_port_write]; |
---|
56 | sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write]; |
---|
57 | |
---|
58 | string rename; |
---|
59 | |
---|
60 | CLOCK = new sc_clock ("clock", 1.0, 0.5); |
---|
61 | NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
---|
62 | |
---|
63 | /******************************************************** |
---|
64 | * Instanciation |
---|
65 | ********************************************************/ |
---|
66 | |
---|
67 | cout << "<" << name << "> Instanciation of _RegisterFile" << endl; |
---|
68 | |
---|
69 | (*(_RegisterFile->in_CLOCK)) (*(CLOCK)); |
---|
70 | (*(_RegisterFile->in_NRESET)) (*(NRESET)); |
---|
71 | |
---|
72 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
---|
73 | { |
---|
74 | (*(_RegisterFile-> in_READ_VAL [i])) (READ_VAL [i]); |
---|
75 | (*(_RegisterFile->out_READ_ACK [i])) (READ_ACK [i]); |
---|
76 | if (_param->_have_port_address == true) |
---|
77 | (*(_RegisterFile-> in_READ_ADDRESS [i])) (READ_ADDRESS [i]); |
---|
78 | (*(_RegisterFile->out_READ_DATA [i])) (READ_DATA [i]); |
---|
79 | } |
---|
80 | |
---|
81 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
---|
82 | { |
---|
83 | (*(_RegisterFile-> in_WRITE_VAL [i])) (WRITE_VAL [i]); |
---|
84 | (*(_RegisterFile->out_WRITE_ACK [i])) (WRITE_ACK [i]); |
---|
85 | if (_param->_have_port_address == true) |
---|
86 | (*(_RegisterFile-> in_WRITE_ADDRESS [i])) (WRITE_ADDRESS [i]); |
---|
87 | (*(_RegisterFile-> in_WRITE_DATA [i])) (WRITE_DATA [i]); |
---|
88 | } |
---|
89 | |
---|
90 | cout << "<" << name << "> Start Simulation ............" << endl; |
---|
91 | Time * _time = new Time(); |
---|
92 | |
---|
93 | /******************************************************** |
---|
94 | * Simulation - Begin |
---|
95 | ********************************************************/ |
---|
96 | |
---|
97 | const bool simulate_read = true; |
---|
98 | const uint32_t nb_request = _param->_nb_word; |
---|
99 | // random init |
---|
100 | const uint32_t grain = 0; |
---|
101 | //const uint32_t grain = static_cast<uint32_t>(time(NULL)); |
---|
102 | |
---|
103 | srand(grain); |
---|
104 | |
---|
105 | // Initialisation |
---|
106 | |
---|
107 | SC_START(0); |
---|
108 | |
---|
109 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
---|
110 | WRITE_VAL [i] .write (0); |
---|
111 | |
---|
112 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
---|
113 | READ_VAL [i] .write (0); |
---|
114 | |
---|
115 | NRESET->write(0); |
---|
116 | |
---|
117 | SC_START(5); |
---|
118 | |
---|
119 | NRESET->write(1); |
---|
120 | |
---|
121 | for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++) |
---|
122 | { |
---|
123 | cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl; |
---|
124 | |
---|
125 | registerfile::Taddress_t nb_val = 0; |
---|
126 | registerfile::Taddress_t nb_ack = 0; |
---|
127 | |
---|
128 | Tdata_t tab_data [_param->_nb_word]; |
---|
129 | registerfile::Taddress_t tab_address [nb_request ]; |
---|
130 | |
---|
131 | for (uint32_t i=0; i<_param->_nb_word; i++) |
---|
132 | tab_data [i]= rand()%(1<<(_param->_size_word-1)); |
---|
133 | for (uint32_t i=0; i<nb_request; i++) |
---|
134 | tab_address [i]= rand()%(1<<(_param->_size_address)); |
---|
135 | |
---|
136 | while (nb_ack < nb_request) |
---|
137 | { |
---|
138 | cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; |
---|
139 | |
---|
140 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
---|
141 | { |
---|
142 | if ((nb_val < nb_request) and |
---|
143 | (WRITE_VAL [num_port].read() == 0)) |
---|
144 | { |
---|
145 | cout << "(" << num_port << ") [" << tab_address[nb_val] << "] <= " << tab_data[tab_address[nb_val]] << endl; |
---|
146 | |
---|
147 | WRITE_VAL [num_port] .write(1); |
---|
148 | WRITE_DATA [num_port] .write(tab_data[tab_address[nb_val]]); |
---|
149 | WRITE_ADDRESS [num_port] .write(tab_address[nb_val]); |
---|
150 | |
---|
151 | nb_val ++; |
---|
152 | |
---|
153 | // Address can be not a multiple of nb_port_write |
---|
154 | if (nb_val >= nb_request) |
---|
155 | break; |
---|
156 | } |
---|
157 | } |
---|
158 | |
---|
159 | SC_START(1); |
---|
160 | |
---|
161 | // reset write_val port |
---|
162 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
---|
163 | { |
---|
164 | if ((WRITE_ACK [num_port].read() == 1) and |
---|
165 | (WRITE_VAL [num_port].read() == 1)) |
---|
166 | { |
---|
167 | WRITE_VAL [num_port] .write(0); |
---|
168 | nb_ack ++; |
---|
169 | } |
---|
170 | } |
---|
171 | |
---|
172 | SC_START(0); |
---|
173 | } |
---|
174 | |
---|
175 | |
---|
176 | if (simulate_read == true) |
---|
177 | { |
---|
178 | cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl; |
---|
179 | |
---|
180 | nb_val = 0; |
---|
181 | nb_ack = 0; |
---|
182 | Tdata_t read_address [_param->_nb_port_read]; |
---|
183 | |
---|
184 | while (nb_ack < nb_request) |
---|
185 | { |
---|
186 | cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; |
---|
187 | |
---|
188 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
---|
189 | { |
---|
190 | if ((nb_val < nb_request) and |
---|
191 | (READ_VAL [num_port].read() == 0)) |
---|
192 | { |
---|
193 | read_address [num_port] = tab_address[nb_val]; |
---|
194 | READ_VAL [num_port].write(1); |
---|
195 | READ_ADDRESS [num_port].write(read_address [num_port]); |
---|
196 | |
---|
197 | nb_val ++; |
---|
198 | |
---|
199 | if (nb_val >= nb_request) |
---|
200 | break; |
---|
201 | } |
---|
202 | } |
---|
203 | |
---|
204 | SC_START(1); |
---|
205 | |
---|
206 | // reset write_val port |
---|
207 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
---|
208 | { |
---|
209 | if ((READ_ACK [num_port].read() == 1) and |
---|
210 | (READ_VAL [num_port].read() == 1)) |
---|
211 | { |
---|
212 | READ_VAL [num_port] .write(0); |
---|
213 | |
---|
214 | cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl; |
---|
215 | |
---|
216 | TEST(Tdata_t,READ_DATA [num_port].read(), tab_data[read_address [num_port]]); |
---|
217 | nb_ack ++; |
---|
218 | } |
---|
219 | } |
---|
220 | |
---|
221 | SC_START(0); |
---|
222 | } |
---|
223 | } |
---|
224 | } |
---|
225 | |
---|
226 | /******************************************************** |
---|
227 | * Simulation - End |
---|
228 | ********************************************************/ |
---|
229 | |
---|
230 | TEST_OK ("End of Simulation"); |
---|
231 | delete _time; |
---|
232 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
---|
233 | |
---|
234 | delete CLOCK; |
---|
235 | delete NRESET; |
---|
236 | #endif |
---|
237 | |
---|
238 | delete _RegisterFile; |
---|
239 | } |
---|