1 | /* |
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2 | * $Id$ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | * Test |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Generic/RegisterFile/SelfTest/include/test.h" |
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10 | #include "Common/include/Test.h" |
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11 | |
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12 | #define NB_ITERATION 1 |
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13 | #define CYCLE_MAX (256*NB_ITERATION) |
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14 | |
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15 | #define LABEL(str) \ |
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16 | { \ |
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17 | cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} " << str << endl; \ |
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18 | } while(0) |
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19 | |
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20 | #define SC_START(cycle) \ |
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21 | do \ |
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22 | { \ |
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23 | if (static_cast<uint32_t>(sc_simulation_time()) > CYCLE_MAX) \ |
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24 | { \ |
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25 | TEST_KO("Maximal cycles Reached"); \ |
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26 | } \ |
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27 | sc_start(cycle); \ |
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28 | } while(0) |
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29 | |
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30 | void test (string name, |
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31 | morpheo::behavioural::generic::registerfile::Parameters * _param) |
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32 | { |
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33 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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34 | |
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35 | #ifdef STATISTICS |
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36 | morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics(5,50); |
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37 | #endif |
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38 | |
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39 | RegisterFile * _RegisterFile = new RegisterFile (name.c_str(), |
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40 | #ifdef STATISTICS |
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41 | _param_stat, |
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42 | #endif |
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43 | _param); |
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44 | |
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45 | #ifdef SYSTEMC |
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46 | /********************************************************************* |
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47 | * Déclarations des signaux |
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48 | *********************************************************************/ |
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49 | sc_clock * CLOCK; |
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50 | sc_signal<Tcontrol_t> * NRESET; |
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51 | |
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52 | sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read]; |
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53 | sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read]; |
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54 | sc_signal<Taddress_t> READ_ADDRESS [_param->_nb_port_read]; |
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55 | sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read]; |
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56 | |
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57 | sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write]; |
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58 | sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write]; |
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59 | sc_signal<Taddress_t> WRITE_ADDRESS [_param->_nb_port_write]; |
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60 | sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write]; |
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61 | |
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62 | string rename; |
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63 | |
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64 | CLOCK = new sc_clock ("clock", 1.0, 0.5); |
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65 | NRESET = new sc_signal<Tcontrol_t> ("NRESET"); |
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66 | |
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67 | /******************************************************** |
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68 | * Instanciation |
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69 | ********************************************************/ |
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70 | |
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71 | cout << "<" << name << "> Instanciation of _RegisterFile" << endl; |
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72 | |
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73 | (*(_RegisterFile->in_CLOCK)) (*(CLOCK)); |
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74 | (*(_RegisterFile->in_NRESET)) (*(NRESET)); |
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75 | |
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76 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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77 | { |
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78 | (*(_RegisterFile-> in_READ_VAL [i])) (READ_VAL [i]); |
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79 | (*(_RegisterFile->out_READ_ACK [i])) (READ_ACK [i]); |
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80 | if (_param->_have_port_address == true) |
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81 | (*(_RegisterFile-> in_READ_ADDRESS [i])) (READ_ADDRESS [i]); |
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82 | (*(_RegisterFile->out_READ_DATA [i])) (READ_DATA [i]); |
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83 | } |
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84 | |
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85 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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86 | { |
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87 | (*(_RegisterFile-> in_WRITE_VAL [i])) (WRITE_VAL [i]); |
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88 | (*(_RegisterFile->out_WRITE_ACK [i])) (WRITE_ACK [i]); |
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89 | if (_param->_have_port_address == true) |
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90 | (*(_RegisterFile-> in_WRITE_ADDRESS [i])) (WRITE_ADDRESS [i]); |
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91 | (*(_RegisterFile-> in_WRITE_DATA [i])) (WRITE_DATA [i]); |
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92 | } |
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93 | |
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94 | cout << "<" << name << "> Start Simulation ............" << endl; |
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95 | Time * _time = new Time(); |
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96 | |
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97 | /******************************************************** |
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98 | * Simulation - Begin |
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99 | ********************************************************/ |
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100 | |
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101 | const bool simulate_read = true; |
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102 | const uint32_t nb_request = _param->_nb_word; |
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103 | // random init |
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104 | const uint32_t grain = 0; |
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105 | //const uint32_t grain = static_cast<uint32_t>(time(NULL)); |
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106 | |
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107 | srand(grain); |
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108 | |
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109 | // Initialisation |
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110 | |
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111 | SC_START(0); |
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112 | |
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113 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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114 | WRITE_VAL [i] .write (0); |
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115 | |
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116 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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117 | READ_VAL [i] .write (0); |
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118 | |
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119 | NRESET->write(0); |
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120 | |
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121 | SC_START(5); |
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122 | |
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123 | NRESET->write(1); |
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124 | |
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125 | for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++) |
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126 | { |
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127 | cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl; |
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128 | |
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129 | Taddress_t nb_val = 0; |
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130 | Taddress_t nb_ack = 0; |
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131 | |
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132 | Tdata_t tab_data [_param->_nb_word]; |
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133 | Taddress_t tab_address [nb_request ]; |
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134 | |
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135 | for (uint32_t i=0; i<_param->_nb_word; i++) |
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136 | tab_data [i]= rand()%(1<<(_param->_size_word-1)); |
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137 | for (uint32_t i=0; i<nb_request; i++) |
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138 | tab_address [i]= rand()%(1<<(_param->_size_address)); |
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139 | |
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140 | while (nb_ack < nb_request) |
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141 | { |
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142 | cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; |
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143 | |
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144 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
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145 | { |
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146 | if ((nb_val < nb_request) and |
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147 | (WRITE_VAL [num_port].read() == 0)) |
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148 | { |
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149 | cout << "(" << num_port << ") [" << tab_address[nb_val] << "] <= " << tab_data[tab_address[nb_val]] << endl; |
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150 | |
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151 | WRITE_VAL [num_port] .write(1); |
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152 | WRITE_DATA [num_port] .write(tab_data[tab_address[nb_val]]); |
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153 | WRITE_ADDRESS [num_port] .write(tab_address[nb_val]); |
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154 | |
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155 | nb_val ++; |
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156 | |
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157 | // Address can be not a multiple of nb_port_write |
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158 | if (nb_val >= nb_request) |
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159 | break; |
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160 | } |
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161 | } |
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162 | |
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163 | SC_START(1); |
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164 | |
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165 | // reset write_val port |
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166 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
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167 | { |
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168 | if ((WRITE_ACK [num_port].read() == 1) and |
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169 | (WRITE_VAL [num_port].read() == 1)) |
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170 | { |
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171 | WRITE_VAL [num_port] .write(0); |
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172 | nb_ack ++; |
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173 | } |
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174 | } |
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175 | |
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176 | SC_START(0); |
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177 | } |
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178 | |
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179 | |
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180 | if (simulate_read == true) |
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181 | { |
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182 | cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl; |
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183 | |
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184 | nb_val = 0; |
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185 | nb_ack = 0; |
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186 | Tdata_t read_address [_param->_nb_port_read]; |
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187 | |
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188 | while (nb_ack < nb_request) |
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189 | { |
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190 | cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; |
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191 | |
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192 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
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193 | { |
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194 | if ((nb_val < nb_request) and |
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195 | (READ_VAL [num_port].read() == 0)) |
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196 | { |
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197 | read_address [num_port] = tab_address[nb_val]; |
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198 | READ_VAL [num_port].write(1); |
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199 | READ_ADDRESS [num_port].write(read_address [num_port]); |
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200 | |
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201 | nb_val ++; |
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202 | |
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203 | if (nb_val >= nb_request) |
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204 | break; |
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205 | } |
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206 | } |
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207 | |
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208 | SC_START(1); |
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209 | |
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210 | // reset write_val port |
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211 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
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212 | { |
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213 | if ((READ_ACK [num_port].read() == 1) and |
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214 | (READ_VAL [num_port].read() == 1)) |
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215 | { |
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216 | READ_VAL [num_port] .write(0); |
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217 | |
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218 | cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl; |
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219 | |
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220 | TEST(Tdata_t,READ_DATA [num_port].read(), tab_data[read_address [num_port]]); |
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221 | nb_ack ++; |
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222 | } |
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223 | } |
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224 | |
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225 | SC_START(0); |
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226 | } |
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227 | } |
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228 | } |
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229 | |
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230 | /******************************************************** |
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231 | * Simulation - End |
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232 | ********************************************************/ |
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233 | |
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234 | TEST_OK ("End of Simulation"); |
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235 | delete _time; |
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236 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
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237 | |
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238 | delete CLOCK; |
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239 | delete NRESET; |
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240 | #endif |
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241 | |
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242 | delete _RegisterFile; |
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243 | } |
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