source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Victim/Victim_Pseudo_LRU/src/Victim_Pseudo_LRU_allocation.cpp

Last change on this file was 112, checked in by rosiere, 15 years ago

1) Stat_list : fix retire old and new register bug
2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step)
3) Model : add class Model (cf Morpheo.sim)
4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array.
5) Script : add distexe.sh
6) Add Comparator, Multiplier, Divider. But this component are not implemented
7) Software : add Dhrystone
  • Property svn:keywords set to Id
File size: 2.5 KB
RevLine 
[10]1/*
2 * $Id: Victim_Pseudo_LRU_allocation.cpp 112 2009-03-18 22:36:26Z rosiere $
3 *
[112]4 * [ Description ]
[10]5 *
6 */
7
[15]8#include "Behavioural/Generic/Victim/Victim_Pseudo_LRU/include/Victim_Pseudo_LRU.h"
[78]9#include "Behavioural/include/Allocation.h"
[10]10
11namespace morpheo {
12namespace behavioural {
13namespace generic {
14namespace victim {
[15]15namespace victim_pseudo_lru {
[10]16
[15]17  void Victim_Pseudo_LRU::allocation (void)
[10]18  {
[82]19    _component   = new Component (_usage);
[10]20
[75]21    Entity * entity = _component->set_entity (_name                 
22                                              ,"Select_Priority_Fixed"
23#ifdef POSITION
24                                              ,COMBINATORY           
25#endif
26                                              );
[10]27   
[42]28    _interfaces = entity->set_interfaces();
[10]29
[112]30    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[42]31    {
[75]32      Interface_fifo * interface = _interfaces->set_interface(""
33#ifdef POSITION
34                                                              , IN  ,WEST, "Generalist interface"
35#endif
36                                                              );
[42]37     
[95]38      in_CLOCK        = interface->set_signal_clk              ("clock" ,1, CLOCK_VHDL_YES);
39      in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
[42]40    }
[10]41
[112]42    // ~~~~~[ Interface : "access" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
[42]43    {
[112]44      ALLOC1_INTERFACE_BEGIN("access",IN,WEST, "Access", _param->_nb_access);
[10]45
[78]46      ALLOC1_VALACK_IN ( in_ACCESS_VAL    ,VAL);
47      ALLOC1_VALACK_OUT(out_ACCESS_ACK    ,ACK);
48      ALLOC1_SIGNAL_IN ( in_ACCESS_HIT    ,"hit"    ,Tcontrol_t,1);
49      ALLOC1_SIGNAL_IN ( in_ACCESS_ADDRESS,"address",Taddress_t,log2(_param->_size_address));
50      ALLOC1_SIGNAL_IN ( in_ACCESS_ENTITY ,"entity" ,Tentity_t ,log2(_param->_nb_entity   ));
51      ALLOC1_SIGNAL_OUT(out_ACCESS_VICTIM ,"victim" ,Tentity_t ,log2(_param->_nb_entity   ));
[112]52
53      ALLOC1_INTERFACE_END(_param->_nb_access);
[42]54    }
[10]55
[88]56    if (usage_is_set(_usage,USE_SYSTEMC))
57      {
[112]58        // -----[ Register ]---------------------------------------------------
59        reg_TABLE = new entry_t *  [_param->_size_table];
60       
61        for (uint32_t i=0; i<_param->_size_table; i++)
62          reg_TABLE [i] = new entry_t (_param->_nb_entity);
63       
64        // -----[ Internal ]---------------------------------------------------
65        ALLOC1(internal_ACCESS_ACK   ,Tcontrol_t,_param->_nb_access);
66        ALLOC1(internal_ACCESS_VICTIM,Tentity_t ,_param->_nb_access);
[88]67      }
[42]68
69#ifdef POSITION
[88]70    if (usage_is_set(_usage,USE_POSITION))
71      _component->generate_file();
[42]72#endif
[10]73  };
74
[15]75}; // end namespace victim_pseudo_lru
[10]76}; // end namespace victim
77}; // end namespace generic
78
79}; // end namespace behavioural
80}; // end namespace morpheo             
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