| 1 | # |
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| 2 | # $Id: Makefile.Synthesis 137 2010-02-16 12:35:48Z rosiere $ |
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| 3 | # |
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| 4 | # [ Description ] |
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| 5 | # |
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| 6 | # Makefile |
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| 7 | # |
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| 8 | |
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| 9 | #-----[ Variables ]---------------------------------------- |
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| 10 | |
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| 11 | DIR_VHDL = . |
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| 12 | WORK_NAME = work |
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| 13 | DIR_WORK = $(DIR_TMP)/$(WORK_NAME) |
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| 14 | |
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| 15 | FPGA_CFG_FILE_LOCAL = mkf.info |
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| 16 | FPGA_CFG_FILE_GLOBAL_DIR = $(DIR_MORPHEO)/Behavioural |
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| 17 | FPGA_CFG_FILE_GLOBAL = configure.mkf |
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| 18 | |
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| 19 | FPGA_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,%,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \ |
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| 20 | $(patsubst $(DIR_CFG_USER)/%.cfg,%,$(wildcard $(DIR_CFG_USER)/*.cfg)) |
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| 21 | |
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| 22 | FPGA_LOG_FILES = $(patsubst $(DIR_CFG_GEN)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_GEN)/*.cfg)) \ |
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| 23 | $(patsubst $(DIR_CFG_USER)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_USER)/*.cfg)) |
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| 24 | |
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| 25 | |
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| 26 | #-----[ Rules ]-------------------------------------------- |
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| 27 | .PRECIOUS : $(DIR_LOG)/%.vhdl.log $(DIR_LOG)/%.sim.log |
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| 28 | |
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| 29 | vhdl : $(EXEC_LOG) |
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| 30 | @\ |
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| 31 | $(MAKE) vhdl_package; \ |
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| 32 | $(MAKE) vhdl_entity; \ |
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| 33 | $(MAKE) vhdl_testbench |
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| 34 | |
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| 35 | vhdl_package : $(DIR_WORK) |
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| 36 | @\ |
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| 37 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Pack.vhdl)); \ |
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| 38 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
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| 39 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) -k $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; |
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| 40 | |
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| 41 | vhdl_testbench : $(DIR_WORK) |
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| 42 | @\ |
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| 43 | $(LS) $(DIR_VHDL)/*_Testbench.vhdl &> /dev/null; \ |
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| 44 | if $(TEST) $$? -eq 0; then \ |
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| 45 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \ |
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| 46 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
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| 47 | if $(TEST) $${#log_files[*]} -ne 0; then \ |
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| 48 | $(MAKE) -k $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; \ |
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| 49 | fi; \ |
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| 50 | fi; |
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| 51 | |
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| 52 | vhdl_entity : $(DIR_WORK) |
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| 53 | @\ |
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| 54 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl|$(GREP_NOT) "(_Pack\.|_Testbench\.)")); \ |
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| 55 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl.log}); \ |
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| 56 | if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) -k $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi; \ |
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| 57 | |
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| 58 | #list : |
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| 59 | # @\ |
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| 60 | # declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*.vhdl|$(GREP_NOT) "(_Pack\.|_Testbench\.)")); \ |
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| 61 | # for file1 in $${vhdl_files[*]}; do \ |
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| 62 | # declare x=$$(basename $${file1} .vhdl); \ |
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| 63 | # declare -i count_x=$($(ECHO) $${x} | ${WC} -m); \ |
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| 64 | # for file2 in $${vhdl_files[*]}; do \ |
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| 65 | # if $(TEST) "$${file1}" != "$${file2}"; then\ |
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| 66 | # declare y=$$(basename $${file2} .vhdl); \ |
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| 67 | # declare -i count_y=$($(ECHO) $${y} | ${WC} -m); \ |
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| 68 | # if $(TEST) $${count_x} -gt $${count_y}; then \ |
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| 69 | # break; \ |
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| 70 | # fi; \ |
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| 71 | # $(ECHO) $${x}; \ |
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| 72 | # fi; \ |
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| 73 | # done; \ |
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| 74 | # done; |
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| 75 | |
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| 76 | sim : vhdl |
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| 77 | @\ |
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| 78 | $(LS) $(DIR_VHDL)/*_Testbench.vhdl &> /dev/null; \ |
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| 79 | if $(TEST) $$? -eq 0; then \ |
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| 80 | declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl)); \ |
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| 81 | declare -a log_files=($${vhdl_files[*]/%.vhdl/.sim.log}); \ |
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| 82 | if $(TEST) $${#log_files[*]} -ne 0; then \ |
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| 83 | $(MAKE) -k $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; \ |
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| 84 | fi; \ |
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| 85 | fi; |
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| 86 | |
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| 87 | fpga : sim |
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| 88 | @\ |
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| 89 | $(ECHO) -e "" > $(FPGA_CFG_FILE_LOCAL); \ |
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| 90 | $(ECHO) "files :::::::: $(FPGA_FILES)"; \ |
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| 91 | for file in $(FPGA_FILES); do \ |
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| 92 | declare -a files=($$($(LS) $$file*.vhdl|$(GREP_NOT) "(_Testbench\.)")); \ |
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| 93 | $(ECHO) -e "# $$file" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 94 | $(ECHO) -e "target_dep\tall\t$$file.ngc" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 95 | $(ECHO) -e "target_dep\t$$file.ngc\t$$file.prj" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 96 | $(ECHO) -e "target_dep\t$$file.prj\t$${files[*]}" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 97 | $(ECHO) -e "" >> $(FPGA_CFG_FILE_LOCAL); \ |
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| 98 | done; \ |
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| 99 | ($(XILINX_ENV); cd $(FPGA_CFG_FILE_GLOBAL_DIR); ./$(FPGA_CFG_FILE_GLOBAL)); \ |
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| 100 | $(MAKE) -k $(FPGA_LOG_FILES); |
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| 101 | |
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| 102 | $(DIR_LOG)/%.fpga.log : |
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| 103 | @\ |
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| 104 | $(ECHO) "Synthetis on FPGA : $*"; \ |
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| 105 | $(XILINX_ENV); $(MAKE) -f Makefile.mkf $*.ngc &> $@; |
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| 106 | |
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| 107 | $(DIR_WORK) : |
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| 108 | @\ |
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| 109 | $(ECHO) "Create work-space : $@"; \ |
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| 110 | mkdir -p $@; \ |
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| 111 | $(MODELTECH_VLIB) $@; \ |
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| 112 | $(MODELTECH_VMAP) $(XILINX_LIBNAME) $(XILINX_LIBDIR); \ |
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| 113 | if $(TEST) $${?} -ne 0; then \ |
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| 114 | $(ECHO) "Xilinx corelib must be compiled to simulation tools"; \ |
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| 115 | $(ECHO) "Run manualy \"$(XILINX_COMPXLIB)\" with $(XILINX_CORELIB) directory"; \ |
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| 116 | fi; |
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| 117 | |
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| 118 | $(DIR_LOG)/%.sim.log : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log |
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| 119 | @\ |
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| 120 | $(ECHO) "VHDL's Simulation : $*"; \ |
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| 121 | $(MODELTECH_VSIM) "$(DIR_WORK).`$(BASENAME) $* |$(UPPERtoLOWER)`" &> $@; \ |
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| 122 | declare -i count=`$(GREP) -ch "Test OK" $@`; \ |
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| 123 | if $(TEST) $$count -ne 0; \ |
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| 124 | then echo " $* ... OK"; \ |
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| 125 | else echo " $* ... KO"; exit 1; \ |
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| 126 | fi; |
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| 127 | |
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| 128 | $(DIR_LOG)/%.vhdl.log : $(DIR_VHDL)/%.vhdl |
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| 129 | @\ |
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| 130 | $(ECHO) "VHDL's Compilation : $*"; \ |
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| 131 | $(MODELTECH_VCOM) -work $(DIR_WORK) $< &> $@; |
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| 132 | |
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| 133 | synthesis_clean : |
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| 134 | @\ |
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| 135 | if $(TEST) -f Makefile.mkf; then $(MAKE) -f Makefile.mkf clean; fi; \ |
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| 136 | $(RM) $(DIR_WORK) transcript Makefile.mkf *wlf* modelsim.ini; |
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| 137 | |
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| 138 | synthesis_clean_all : synthesis_clean |
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| 139 | |
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| 140 | synthesis_help : |
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| 141 | @\ |
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| 142 | $(ECHO) " -----[ Synthesis ]----------------------------------";\ |
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| 143 | $(ECHO) "";\ |
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| 144 | $(ECHO) " * vhdl : compile all vhdl's file";\ |
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| 145 | $(ECHO) " * sim : simulate all testbench's file";\ |
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| 146 | $(ECHO) " * fpga : synthetis with fpga's tools";\ |
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| 147 | $(ECHO) ""; |
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