Last change
on this file since 44 was
44,
checked in by rosiere, 17 years ago
|
Modification des classes d'encapsulation des interfaces.
Stable sur tous les composants actuels
|
File size:
1.3 KB
|
Line | |
---|
1 | # |
---|
2 | # $Id$ |
---|
3 | # |
---|
4 | # [ Description ] |
---|
5 | # |
---|
6 | |
---|
7 | #-----[ Simulator ]---------------------------------------- |
---|
8 | SIMULATOR = systemcass |
---|
9 | |
---|
10 | # 3 simulators : |
---|
11 | # systemc - SystemC |
---|
12 | # systemcass - SystemCASS |
---|
13 | # systemcass_deps - SystemCASS, and use port dependency information instead of sensitivity list |
---|
14 | |
---|
15 | #-----[ Flags ]-------------------------------------------- |
---|
16 | FLAGS = -DSYSTEMC \ |
---|
17 | -DVHDL \ |
---|
18 | -DVHDL_TESTBENCH \ |
---|
19 | -DVHDL_TESTBENCH_ASSERT \ |
---|
20 | -DDEBUG=DEBUG_NONE |
---|
21 | |
---|
22 | # -DCONFIGURATION \ |
---|
23 | # -DSTATISTICS \ |
---|
24 | # -DPOSITION \ |
---|
25 | |
---|
26 | # Flags : |
---|
27 | # DEBUG={level} - Print Debug Message |
---|
28 | # SYSTEMC - To generate a systemc's model |
---|
29 | # VHDL - To generate a vhdl's models |
---|
30 | # VHDL_TESTBENCH (need SYSTEMC) - In the simulation, generate two testbench's file (input and ouput) to validate the vhdl's model |
---|
31 | # VHDL_TESTBENCH_ASSERT (need SYSTEMC) - In the simulation, generate in testbench's file an serie of assert |
---|
32 | # STATISTICS (need SYSTEMC) - In the simulation, generate a statistics's file |
---|
33 | # POSITION - To generate a position's files (it's input of viewer) |
---|
34 | # CONFIGURATION - To generate a configuration's file (it's input of viewer and generator) |
---|
Note: See
TracBrowser
for help on using the repository browser.