1 | #ifdef VHDL_TESTBENCH |
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2 | /* |
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3 | * $Id$ |
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4 | * |
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5 | * [ Description ] |
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6 | * |
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7 | */ |
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8 | |
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9 | #include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Meta_Predictor_Glue/include/Meta_Predictor_Glue.h" |
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10 | |
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11 | namespace morpheo { |
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12 | namespace behavioural { |
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13 | namespace stage_1_ifetch { |
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14 | namespace predictor { |
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15 | namespace meta_predictor { |
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16 | namespace meta_predictor_glue { |
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17 | |
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18 | |
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19 | void Meta_Predictor_Glue::vhdl_testbench_transition () |
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20 | { |
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21 | log_printf(FUNC,Meta_Predictor_Glue,"vhdl_testbench_transition","Begin"); |
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22 | |
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23 | // Evaluation before read the ouput signal |
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24 | sc_start(0); |
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25 | |
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26 | // In order with file Meta_Predictor_Glue_vhdl_testbench_port.cpp |
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27 | // Warning : if a output depend of a subcomponent, take directly the port of subcomponent |
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28 | // (because we have no control on the ordonnancer's policy) |
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29 | |
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30 | for (uint32_t i=0; i<_param._nb_prediction; i++) |
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31 | { |
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32 | if (_param._have_meta_predictor) |
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33 | { |
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34 | _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_0_ACK [i])); |
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35 | _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_1_ACK [i])); |
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36 | } |
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37 | _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_2_ACK [i])); |
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38 | _vhdl_testbench->add_output(PORT_READ(out_PREDICT_ACK [i])); |
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39 | |
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40 | if (_param._have_meta_predictor) |
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41 | { |
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42 | if (_param._predictor_0_have_bht) |
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43 | _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_0_BHT_HISTORY [i])); |
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44 | if (_param._predictor_0_have_pht) |
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45 | _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_0_PHT_HISTORY [i])); |
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46 | if (_param._predictor_1_have_bht) |
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47 | _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_1_BHT_HISTORY [i])); |
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48 | if (_param._predictor_1_have_pht) |
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49 | _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_1_PHT_HISTORY [i])); |
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50 | } |
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51 | if (_param._predictor_2_have_bht) |
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52 | _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_2_BHT_HISTORY [i])); |
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53 | if (_param._predictor_2_have_pht) |
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54 | _vhdl_testbench->add_input (PORT_READ( in_PREDICT_PREDICTOR_2_PHT_HISTORY [i])); |
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55 | |
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56 | _vhdl_testbench->add_output(PORT_READ(out_PREDICT_HISTORY [i])); |
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57 | _vhdl_testbench->add_output(PORT_READ(out_PREDICT_DIRECTION [i])); |
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58 | } |
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59 | |
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60 | for (uint32_t i=0; i<_param._nb_branch_complete; i++) |
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61 | { |
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62 | if (_param._have_meta_predictor) |
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63 | { |
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64 | _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_VAL [i])); |
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65 | _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_2_VAL [i])); |
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66 | |
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67 | _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_PREDICTOR_0_ACK [i])); |
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68 | _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_PREDICTOR_1_ACK [i])); |
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69 | } |
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70 | _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_PREDICTOR_2_ACK [i])); |
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71 | _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_ACK [i])); |
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72 | |
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73 | if (_param._have_meta_predictor) |
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74 | { |
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75 | if (_param._predictor_0_have_bht) |
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76 | _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY [i])); |
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77 | if (_param._predictor_0_have_pht) |
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78 | _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY [i])); |
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79 | if (_param._predictor_1_have_bht) |
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80 | _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY [i])); |
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81 | if (_param._predictor_1_have_pht) |
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82 | _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY [i])); |
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83 | } |
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84 | if (_param._predictor_2_have_bht) |
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85 | _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY [i])); |
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86 | if (_param._predictor_2_have_pht) |
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87 | _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY [i])); |
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88 | |
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89 | _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_HISTORY [i])); |
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90 | if (_param._have_meta_predictor) |
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91 | { |
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92 | _vhdl_testbench->add_input (PORT_READ( in_BRANCH_COMPLETE_DIRECTION [i])); |
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93 | _vhdl_testbench->add_output(PORT_READ(out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION [i])); |
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94 | } |
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95 | } |
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96 | |
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97 | // add_test : |
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98 | // - True : the cycle must be compare with the output of systemC |
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99 | // - False : no test |
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100 | _vhdl_testbench->add_test(true); |
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101 | |
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102 | _vhdl_testbench->new_cycle (); // always at the end |
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103 | |
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104 | log_printf(FUNC,Meta_Predictor_Glue,"vhdl_testbench_transition","End"); |
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105 | }; |
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106 | |
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107 | }; // end namespace meta_predictor_glue |
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108 | }; // end namespace meta_predictor |
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109 | }; // end namespace predictor |
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110 | }; // end namespace stage_1_ifetch |
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111 | |
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112 | }; // end namespace behavioural |
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113 | }; // end namespace morpheo |
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114 | #endif |
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