1 | /* |
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2 | * $Id$ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | * Test |
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7 | */ |
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8 | |
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9 | #define NB_ITERATION 1024 |
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10 | |
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11 | #include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Branch_History_Table/SelfTest/include/test.h" |
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12 | #include "Include/BitManipulation.h" |
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13 | #include "Include/Test.h" |
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14 | |
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15 | void test (string name, |
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16 | morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::branch_history_table::Parameters param) |
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17 | { |
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18 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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19 | |
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20 | try |
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21 | { |
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22 | cout << param.print(1); |
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23 | param.test(); |
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24 | } |
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25 | catch (morpheo::ErrorMorpheo & error) |
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26 | { |
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27 | cout << "<" << name << "> : " << error.what (); |
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28 | return; |
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29 | } |
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30 | catch (...) |
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31 | { |
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32 | cerr << "<" << name << "> : This test must generate a error" << endl; |
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33 | exit (EXIT_FAILURE); |
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34 | } |
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35 | |
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36 | Branch_History_Table * _Branch_History_Table = new Branch_History_Table (name.c_str(), |
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37 | #ifdef STATISTICS |
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38 | morpheo::behavioural::Parameters_Statistics(5,50), |
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39 | #endif |
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40 | param); |
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41 | |
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42 | #ifdef SYSTEMC |
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43 | |
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44 | /********************************************************************* |
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45 | * Déclarations des signaux |
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46 | *********************************************************************/ |
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47 | sc_clock CLOCK ("clock", 1.0, 0.5); |
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48 | sc_signal<Tcontrol_t> NRESET; |
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49 | sc_signal<Tcontrol_t> PREDICT_VAL [param._nb_prediction]; |
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50 | sc_signal<Tcontrol_t> PREDICT_ACK [param._nb_prediction]; |
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51 | sc_signal<Taddress_t> PREDICT_ADDRESS [param._nb_prediction]; |
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52 | sc_signal<Thistory_t> PREDICT_HISTORY [param._nb_prediction]; |
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53 | |
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54 | sc_signal<Tcontrol_t> BRANCH_COMPLETE_VAL [param._nb_branch_complete]; |
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55 | sc_signal<Tcontrol_t> BRANCH_COMPLETE_ACK [param._nb_branch_complete]; |
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56 | sc_signal<Taddress_t> BRANCH_COMPLETE_ADDRESS [param._nb_branch_complete]; |
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57 | sc_signal<Thistory_t> BRANCH_COMPLETE_HISTORY [param._nb_branch_complete]; |
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58 | sc_signal<Tcontrol_t> BRANCH_COMPLETE_DIRECTION [param._nb_branch_complete]; |
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59 | |
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60 | /******************************************************** |
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61 | * Instanciation |
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62 | ********************************************************/ |
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63 | |
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64 | cout << "<" << name << "> Instanciation of _Branch_History_Table" << endl; |
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65 | |
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66 | (*(_Branch_History_Table->in_CLOCK)) (CLOCK); |
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67 | (*(_Branch_History_Table->in_NRESET)) (NRESET); |
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68 | |
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69 | for (uint32_t i=0; i<param._nb_prediction; i++) |
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70 | { |
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71 | (*(_Branch_History_Table-> in_PREDICT_VAL [i])) (PREDICT_VAL [i]); |
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72 | (*(_Branch_History_Table->out_PREDICT_ACK [i])) (PREDICT_ACK [i]); |
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73 | (*(_Branch_History_Table-> in_PREDICT_ADDRESS [i])) (PREDICT_ADDRESS [i]); |
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74 | (*(_Branch_History_Table->out_PREDICT_HISTORY [i])) (PREDICT_HISTORY [i]); |
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75 | } |
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76 | |
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77 | for (uint32_t i=0; i<param._nb_branch_complete; i++) |
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78 | { |
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79 | (*(_Branch_History_Table-> in_BRANCH_COMPLETE_VAL [i])) (BRANCH_COMPLETE_VAL [i]); |
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80 | (*(_Branch_History_Table->out_BRANCH_COMPLETE_ACK [i])) (BRANCH_COMPLETE_ACK [i]); |
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81 | (*(_Branch_History_Table-> in_BRANCH_COMPLETE_ADDRESS [i])) (BRANCH_COMPLETE_ADDRESS [i]); |
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82 | (*(_Branch_History_Table-> in_BRANCH_COMPLETE_HISTORY [i])) (BRANCH_COMPLETE_HISTORY [i]); |
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83 | (*(_Branch_History_Table-> in_BRANCH_COMPLETE_DIRECTION [i])) (BRANCH_COMPLETE_DIRECTION [i]); |
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84 | } |
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85 | |
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86 | /******************************************************** |
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87 | * Simulation - Begin |
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88 | ********************************************************/ |
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89 | |
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90 | cout << "<" << name << "> Start Simulation ............" << endl; |
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91 | // Initialisation |
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92 | sc_start(0); |
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93 | |
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94 | srand(0); |
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95 | //srand(time(NULL)); |
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96 | |
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97 | |
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98 | _Branch_History_Table->vhdl_testbench_label("Initialisation"); |
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99 | cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl; |
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100 | |
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101 | NRESET.write(1); |
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102 | for (uint32_t i=0; i<param._nb_prediction; i++) |
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103 | PREDICT_VAL [i].write(0); |
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104 | for (uint32_t i=0; i<param._nb_branch_complete; i++) |
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105 | BRANCH_COMPLETE_VAL [i].write(0); |
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106 | |
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107 | // Initialisation of Register |
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108 | uint32_t num_port_branch_complete = 0; |
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109 | uint32_t num_port_predict = 0; |
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110 | Taddress_t address = 0; |
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111 | Thistory_t history = 0; |
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112 | Thistory_t mask = gen_mask <Thistory_t> (param._size_shifter); |
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113 | Tcontrol_t direction = 0; |
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114 | |
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115 | while (address<param._nb_shifter) |
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116 | { |
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117 | BRANCH_COMPLETE_VAL [0].write(1); |
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118 | BRANCH_COMPLETE_ADDRESS [0].write(address); |
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119 | BRANCH_COMPLETE_HISTORY [0].write(0); |
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120 | BRANCH_COMPLETE_DIRECTION [0].write(0); |
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121 | |
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122 | sc_start(1); |
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123 | |
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124 | if (BRANCH_COMPLETE_ACK[0].read()==1) |
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125 | address++; |
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126 | } |
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127 | |
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128 | BRANCH_COMPLETE_VAL [0].write(0); |
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129 | sc_start(0); |
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130 | |
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131 | _Branch_History_Table->vhdl_testbench_label("Loop of Test"); |
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132 | cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl; |
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133 | |
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134 | for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++) |
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135 | { |
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136 | _Branch_History_Table->vhdl_testbench_label("Iteration "+toString(iteration)); |
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137 | num_port_branch_complete = rand() % param._nb_branch_complete; |
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138 | num_port_predict = rand() % param._nb_prediction ; |
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139 | address = rand() % param._nb_shifter ; |
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140 | history = rand() % (1<<param._size_shifter) ; |
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141 | direction = rand() % 2; |
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142 | |
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143 | cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} ["+toString(num_port_branch_complete)+"]" << endl |
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144 | << hex |
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145 | << " - address : " << address << endl |
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146 | << " - history old : " << history << endl |
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147 | << " - direction : " << direction<< endl; |
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148 | |
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149 | BRANCH_COMPLETE_VAL [num_port_branch_complete].write(1); |
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150 | BRANCH_COMPLETE_ADDRESS [num_port_branch_complete].write(address); |
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151 | BRANCH_COMPLETE_HISTORY [num_port_branch_complete].write(history); |
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152 | BRANCH_COMPLETE_DIRECTION [num_port_branch_complete].write(direction); |
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153 | |
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154 | // Wait Ack |
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155 | do |
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156 | { |
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157 | sc_start(1); |
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158 | } |
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159 | while (BRANCH_COMPLETE_ACK[num_port_branch_complete].read()!=1); |
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160 | |
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161 | BRANCH_COMPLETE_VAL [num_port_branch_complete].write(0); |
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162 | PREDICT_VAL [num_port_predict ].write(1); |
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163 | PREDICT_ADDRESS [num_port_predict ].write(address); |
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164 | |
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165 | history = ((history<<1)&mask)|direction; |
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166 | |
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167 | // Wait Ack |
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168 | do |
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169 | { |
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170 | sc_start(1); |
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171 | } |
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172 | while (PREDICT_ACK [num_port_predict ].read()!=1); |
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173 | |
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174 | PREDICT_VAL [num_port_predict ].write(0); |
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175 | |
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176 | cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} ["+toString(num_port_predict)+"]" << endl |
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177 | << " - history new : " << PREDICT_HISTORY [num_port_predict].read() << endl; |
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178 | |
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179 | TEST(Thistory_t,PREDICT_HISTORY [num_port_predict].read(),history); |
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180 | |
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181 | cout << dec; |
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182 | } |
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183 | |
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184 | /******************************************************** |
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185 | * Simulation - End |
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186 | ********************************************************/ |
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187 | |
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188 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
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189 | |
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190 | #endif |
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191 | |
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192 | delete _Branch_History_Table; |
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193 | } |
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