[2] | 1 | #ifdef VHDL |
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| 2 | /* |
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| 3 | * $Id$ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/Pattern_History_Table/include/Pattern_History_Table.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace stage_1_ifetch { |
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| 14 | namespace predictor { |
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| 15 | namespace meta_predictor { |
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| 16 | namespace two_level_branch_predictor { |
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| 17 | namespace pattern_history_table { |
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| 18 | |
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| 19 | |
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| 20 | void Pattern_History_Table::vhdl_body (Vhdl & vhdl) |
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| 21 | { |
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| 22 | log_printf(FUNC,Pattern_History_Table,"vhdl_body","Begin"); |
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| 23 | |
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| 24 | vhdl.set_body ("-- Output : always at '1'"); |
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| 25 | for (uint32_t i=0; i<_param._nb_branch_complete; i++) |
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| 26 | vhdl.set_body ("out_BRANCH_COMPLETE_ACK_"+toString(i)+" <= '1';"); |
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| 27 | for (uint32_t i=0; i<_param._nb_prediction ; i++) |
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| 28 | vhdl.set_body ("out_PREDICT_ACK_"+toString(i)+" <= '1';"); |
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| 29 | vhdl.set_body (""); |
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| 30 | |
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| 31 | list<string> list_port_map; |
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| 32 | |
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| 33 | for (uint32_t i=0; i<_param._nb_branch_complete; i++) |
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| 34 | { |
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| 35 | vhdl.set_body_component_port_map (list_port_map," in_COUNTER_DATA_"+toString(i)+" "," in_BRANCH_COMPLETE_HISTORY_"+toString(i)); |
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[3] | 36 | vhdl.set_body_component_port_map (list_port_map," in_COUNTER_ADDSUB_"+toString(i)+" "," in_BRANCH_COMPLETE_DIRECTION_"+toString(i) ); |
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[2] | 37 | vhdl.set_body_component_port_map (list_port_map,"out_COUNTER_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i)); |
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| 38 | } |
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| 39 | vhdl.set_body_component ("component_Counter",_name+"_Counter",list_port_map); |
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| 40 | |
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| 41 | |
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| 42 | list_port_map.clear(); |
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| 43 | vhdl.set_body_component_port_map (list_port_map,"in_CLOCK","in_CLOCK"); |
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| 44 | for (uint32_t i=0; i<_param._nb_prediction; i++) |
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| 45 | { |
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| 46 | vhdl.set_body_component_port_map (list_port_map," in_READ_ENABLE_"+toString(i)+" "," in_PREDICT_VAL_"+toString(i)); |
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| 47 | vhdl.set_body_component_port_map (list_port_map," in_READ_ADDRESS_"+toString(i)+" "," in_PREDICT_ADDRESS_"+toString(i)); |
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| 48 | vhdl.set_body_component_port_map (list_port_map,"out_READ_DATA_"+toString(i)+" ","out_PREDICT_HISTORY_"+toString(i)); |
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| 49 | } |
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| 50 | |
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| 51 | for (uint32_t i=0; i<_param._nb_branch_complete; i++) |
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| 52 | { |
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| 53 | vhdl.set_body_component_port_map (list_port_map," in_WRITE_ENABLE_"+toString(i)+" "," in_BRANCH_COMPLETE_VAL_"+toString(i)+""); |
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| 54 | vhdl.set_body_component_port_map (list_port_map," in_WRITE_ADDRESS_"+toString(i)+""," in_BRANCH_COMPLETE_ADDRESS_"+toString(i)); |
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| 55 | vhdl.set_body_component_port_map (list_port_map," in_WRITE_DATA_"+toString(i)+" ","signal_BRANCH_COMPLETE_HISTORY_"+toString(i)); |
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| 56 | } |
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| 57 | vhdl.set_body_component ("component_RegisterFile",_name+"_RegisterFile",list_port_map); |
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| 58 | |
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| 59 | log_printf(FUNC,Pattern_History_Table,"vhdl_body","End"); |
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| 60 | }; |
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| 61 | |
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| 62 | }; // end namespace pattern_history_table |
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| 63 | }; // end namespace two_level_branch_predictor |
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| 64 | }; // end namespace meta_predictor |
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| 65 | }; // end namespace predictor |
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| 66 | }; // end namespace stage_1_ifetch |
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| 67 | |
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| 68 | }; // end namespace behavioural |
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| 69 | }; // end namespace morpheo |
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| 70 | #endif |
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