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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/src/test.cpp @ 15

Last change on this file since 15 was 15, checked in by rosiere, 17 years ago
Interface normalisé Début du banc de registres multi niveaux
File size: 11.4 KB

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1	/*
2	* $Id$
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 512
10
11	#include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/Two_Level_Branch_Predictor/SelfTest/include/test.h"
12	#include "Include/Test.h"
13	#include "Include/BitManipulation.h"
14	void test (string name,
15	morpheo::behavioural::stage_1_ifetch::predictor::meta_predictor::two_level_branch_predictor::Parameters param)
16	{
17	cout << "<" << name << "> : Simulation SystemC" << endl;
18
19	Two_Level_Branch_Predictor * _Two_Level_Branch_Predictor = new Two_Level_Branch_Predictor (name.c_str(),
20	#ifdef STATISTICS
21	morpheo::behavioural::Parameters_Statistics(5,50),
22	#endif
23	param);
24
25	#ifdef SYSTEMC
26
27	/*********************************************************************
28	* Déclarations des signaux
29	*********************************************************************/
30	sc_clock * CLOCK;
31	sc_signal<Tcontrol_t> * NRESET;
32
33	sc_signal<Tcontrol_t> * PREDICT_VAL [param._nb_prediction];
34	sc_signal<Tcontrol_t> * PREDICT_ACK [param._nb_prediction];
35	sc_signal<Taddress_t> * PREDICT_ADDRESS [param._nb_prediction];
36	sc_signal<Tbht_history_t> * PREDICT_BHT_HISTORY [param._nb_prediction];
37	sc_signal<Tpht_history_t> * PREDICT_PHT_HISTORY [param._nb_prediction];
38
39	sc_signal<Tcontrol_t> * BRANCH_COMPLETE_VAL [param._nb_branch_complete];
40	sc_signal<Tcontrol_t> * BRANCH_COMPLETE_ACK [param._nb_branch_complete];
41	sc_signal<Taddress_t> * BRANCH_COMPLETE_ADDRESS [param._nb_branch_complete];
42	sc_signal<Tbht_history_t> * BRANCH_COMPLETE_BHT_HISTORY [param._nb_branch_complete];
43	sc_signal<Tpht_history_t> * BRANCH_COMPLETE_PHT_HISTORY [param._nb_branch_complete];
44	sc_signal<Tcontrol_t> * BRANCH_COMPLETE_DIRECTION [param._nb_branch_complete];
45
46	// Rename signal
47
48	string rename;
49
50	CLOCK = new sc_clock ("clock", 1.0, 0.5);
51	NRESET = new sc_signal<Tcontrol_t> ("NRESET");
52
53	for (uint32_t i=0; i<param._nb_prediction; i++)
54	{
55	rename = "PREDICT_VAL_" +toString(i);
56	PREDICT_VAL [i] = new sc_signal<Tcontrol_t> (rename.c_str());
57	rename = "PREDICT_ACK_" +toString(i);
58	PREDICT_ACK [i] = new sc_signal<Tcontrol_t> (rename.c_str());
59	rename = "PREDICT_ADDRESS_" +toString(i);
60	PREDICT_ADDRESS [i] = new sc_signal<Taddress_t> (rename.c_str());
61	rename = "PREDICT_BHT_HISTORY_"+toString(i);
62	PREDICT_BHT_HISTORY [i] = new sc_signal<Tbht_history_t> (rename.c_str());
63	rename = "PREDICT_PHT_HISTORY_"+toString(i);
64	PREDICT_PHT_HISTORY [i] = new sc_signal<Tpht_history_t> (rename.c_str());
65	}
66
67	for (uint32_t i=0; i<param._nb_branch_complete; i++)
68	{
69	rename = "BRANCH_COMPLETE_VAL_" +toString(i);
70	BRANCH_COMPLETE_VAL [i] = new sc_signal<Tcontrol_t> (rename.c_str());
71	rename = "BRANCH_COMPLETE_ACK_" +toString(i);
72	BRANCH_COMPLETE_ACK [i] = new sc_signal<Tcontrol_t> (rename.c_str());
73	rename = "BRANCH_COMPLETE_ADDRESS_" +toString(i);
74	BRANCH_COMPLETE_ADDRESS [i] = new sc_signal<Taddress_t> (rename.c_str());
75	rename = "BRANCH_COMPLETE_BHT_HISTORY_"+toString(i);
76	BRANCH_COMPLETE_BHT_HISTORY [i] = new sc_signal<Tbht_history_t> (rename.c_str());
77	rename = "BRANCH_COMPLETE_PHT_HISTORY_"+toString(i);
78	BRANCH_COMPLETE_PHT_HISTORY [i] = new sc_signal<Tpht_history_t> (rename.c_str());
79	rename = "BRANCH_COMPLETE_DIRECTION_" +toString(i);
80	BRANCH_COMPLETE_DIRECTION [i] = new sc_signal<Tcontrol_t> (rename.c_str());
81	}
82
83	/********************************************************
84	* Instanciation
85	********************************************************/
86
87	cout << "<" << name << "> Instanciation of _Two_Level_Branch_Predictor" << endl;
88
89	((_Two_Level_Branch_Predictor->in_CLOCK )) ((CLOCK ));
90	((_Two_Level_Branch_Predictor->in_NRESET)) ((NRESET));
91
92	for (uint32_t i=0; i<param._nb_prediction; i++)
93	{
94	((_Two_Level_Branch_Predictor-> in_PREDICT_VAL [i])) ((PREDICT_VAL [i]));
95	((_Two_Level_Branch_Predictor->out_PREDICT_ACK [i])) ((PREDICT_ACK [i]));
96	((_Two_Level_Branch_Predictor-> in_PREDICT_ADDRESS [i])) ((PREDICT_ADDRESS [i]));
97	if (param._have_bht)
98	((_Two_Level_Branch_Predictor->out_PREDICT_BHT_HISTORY [i])) ((PREDICT_BHT_HISTORY [i]));
99	if (param._have_pht)
100	((_Two_Level_Branch_Predictor->out_PREDICT_PHT_HISTORY [i])) ((PREDICT_PHT_HISTORY [i]));
101	}
102
103	for (uint32_t i=0; i<param._nb_branch_complete; i++)
104	{
105	((_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_VAL [i])) ((BRANCH_COMPLETE_VAL [i]));
106	((_Two_Level_Branch_Predictor->out_BRANCH_COMPLETE_ACK [i])) ((BRANCH_COMPLETE_ACK [i]));
107	((_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_ADDRESS [i])) ((BRANCH_COMPLETE_ADDRESS [i]));
108	if (param._have_bht)
109	((_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_BHT_HISTORY [i])) ((BRANCH_COMPLETE_BHT_HISTORY [i]));
110	if (param._have_pht)
111	((_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_PHT_HISTORY [i])) ((BRANCH_COMPLETE_PHT_HISTORY [i]));
112	((_Two_Level_Branch_Predictor-> in_BRANCH_COMPLETE_DIRECTION [i])) ((BRANCH_COMPLETE_DIRECTION [i]));
113	}
114
115	/********************************************************
116	* Simulation - Begin
117	********************************************************/
118
119	cout << "<" << name << "> Start Simulation ............" << endl;
120	// Initialisation
121
122	const uint32_t seed = 0;
123	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
124
125	srand(seed);
126
127	const uint32_t num_port_predict = rand()%param._nb_prediction;
128	const uint32_t num_port_branch_complete = rand()%param._nb_branch_complete;
129	const Taddress_t address = rand()%param._size_address;
130	Tcontrol_t direction;
131
132	sc_start(0);
133
134	for (uint32_t i=0; i<param._nb_prediction; i++)
135	PREDICT_VAL [i]->write(0);
136	for (uint32_t i=0; i<param._nb_branch_complete; i++)
137	BRANCH_COMPLETE_VAL [i]->write(0);
138
139	_Two_Level_Branch_Predictor->vhdl_testbench_label("Initialisation");
140	cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Initialisation" << endl;
141
142	// Step 1
143	BRANCH_COMPLETE_VAL [num_port_branch_complete]->write(1);
144	BRANCH_COMPLETE_DIRECTION [num_port_branch_complete]->write(0);
145
146	if (param._have_pht)
147	{
148	// Step 1.1 -> pattern_history_table
149
150	// Step 1.1.1 compute number of group.
151	uint32_t size_address_shift=0;
152
153	if (param._have_bht)
154	size_address_shift=param._param_two_level_branch_predictor_glue->_pht_size_address_shift;
155
156	uint32_t nb_group = (1<<size_address_shift);
157	uint32_t nb_reg_by_group = (1<<(param._pht_size_address-size_address_shift));
158
159	_Two_Level_Branch_Predictor->vhdl_testbench_label("Init pht");
160	cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Init pht" << endl;
161
162	BRANCH_COMPLETE_PHT_HISTORY [num_port_branch_complete]->write(0);
163
164	// Step 1.1.2 for all group ...
165	for (uint32_t i=0; i<nb_group; i++)
166	{
167	if (param._have_bht)
168	BRANCH_COMPLETE_BHT_HISTORY [num_port_branch_complete]->write(i);
169
170	for (uint32_t j=0; j<nb_reg_by_group; j++)
171	{
172	BRANCH_COMPLETE_ADDRESS [num_port_branch_complete]->write(j);
173
174	sc_start(1);
175
176	// wait ackwolegde
177	while (BRANCH_COMPLETE_ACK [num_port_branch_complete] -> read() == 0)
178	sc_start(1);
179	}
180	}
181	}
182
183	if (param._have_bht)
184	{
185	// Step 1.2 -> branch_history_table
186	BRANCH_COMPLETE_BHT_HISTORY [num_port_branch_complete]->write(0);
187
188	_Two_Level_Branch_Predictor->vhdl_testbench_label("Init bht");
189	cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Init bht" << endl;
190
191	for (uint32_t i=0; i<param._bht_nb_shifter; i++)
192	{
193	BRANCH_COMPLETE_ADDRESS [num_port_branch_complete]->write(i);
194
195	sc_start(1);
196	}
197
198	// wait ackwolegde
199	while (BRANCH_COMPLETE_ACK [num_port_branch_complete] -> read() == 0)
200	sc_start(1);
201	}
202
203	// Step 2
204	BRANCH_COMPLETE_VAL [num_port_branch_complete]->write(0);
205	PREDICT_ADDRESS [num_port_predict ]->write(address);
206	BRANCH_COMPLETE_ADDRESS [num_port_branch_complete]->write(address);
207
208	_Two_Level_Branch_Predictor->vhdl_testbench_label("Loop of Test");
209	cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Loop of Test" << endl
210	<< " * predict_address : " << hex << address << dec << endl;
211
212	// A lot of prediction
213	Tbht_history_t bht_history = 0;
214	Tpht_history_t pht_history [1<<param._bht_size_shifter];
215
216	for (uint32_t i=0; i<static_cast<uint32_t>(1<<param._bht_size_shifter); i++)
217	pht_history [i] = 0;
218
219	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
220	{
221	_Two_Level_Branch_Predictor->vhdl_testbench_label("Iteration "+toString(iteration));
222
223	cout << "{"+toString(static_cast<uint32_t>(sc_simulation_time()))+"} Predict : bht_history " << bht_history << " - pht_history " << pht_history[bht_history] << endl;
224
225
226	// Ask a new prediction
227	PREDICT_VAL [num_port_predict ]->write(1);
228
229	sc_start(1);
230
231	// wait ackwolegde
232	while (PREDICT_ACK [num_port_predict] -> read() == 0)
233	sc_start(1);
234	PREDICT_ACK [num_port_predict ]->write(0);
235
236	sc_start(0);
237
238	// Test
239	if (param._have_bht)
240	TEST(Tbht_history_t,bht_history ,PREDICT_BHT_HISTORY[num_port_predict]->read());
241	if (param._have_pht)
242	TEST(Tpht_history_t,pht_history[bht_history],PREDICT_PHT_HISTORY[num_port_predict]->read());
243
244	// update
245	direction = ((rand()%2)==1);
246
247	BRANCH_COMPLETE_VAL [num_port_branch_complete]->write(1);
248	if (param._have_bht)
249	BRANCH_COMPLETE_BHT_HISTORY [num_port_branch_complete]->write(bht_history );
250
251
252	if (param._have_pht)
253	BRANCH_COMPLETE_PHT_HISTORY [num_port_branch_complete]->write(pht_history[bht_history]);
254	BRANCH_COMPLETE_DIRECTION [num_port_branch_complete]->write(direction);
255
256	if (param._have_pht)
257	if (direction == 0)
258	{
259	if (pht_history[bht_history] > 0)
260	pht_history[bht_history] --;
261	}
262	else
263	{
264	if (pht_history[bht_history] < (static_cast<Tpht_history_t>(1<<param._pht_size_counter)-1))
265	pht_history[bht_history] ++;
266	}
267
268	if (param._have_bht)
269	bht_history = (((bht_history) << 1) \| direction) & gen_mask<Tbht_history_t>(param._bht_size_shifter);
270
271	sc_start(1);
272
273	// wait ackwolegde
274	while (BRANCH_COMPLETE_ACK [num_port_branch_complete] -> read() == 0)
275	sc_start(1);
276
277	BRANCH_COMPLETE_VAL [num_port_branch_complete]->write(0);
278	}
279
280	/********************************************************
281	* Simulation - End
282	********************************************************/
283
284	cout << "<" << name << "> ............ Stop Simulation" << endl;
285
286	#endif
287
288	delete _Two_Level_Branch_Predictor;
289	}

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