[5] | 1 | #ifdef VHDL |
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| 2 | /* |
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| 3 | * $Id$ |
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| 4 | * |
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| 5 | * [ Description ] |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #include "Behavioural/Stage_1_Ifetch/Predictor/Meta_Predictor/include/Meta_Predictor.h" |
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| 10 | |
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| 11 | namespace morpheo { |
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| 12 | namespace behavioural { |
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| 13 | namespace stage_1_ifetch { |
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| 14 | namespace predictor { |
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| 15 | namespace meta_predictor { |
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| 16 | |
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| 17 | |
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| 18 | void Meta_Predictor::vhdl_body (Vhdl & vhdl) |
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| 19 | { |
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| 20 | log_printf(FUNC,Meta_Predictor,"vhdl_body","Begin"); |
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| 21 | vhdl.set_body (""); |
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| 22 | |
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| 23 | list<string> list_port_map; |
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| 24 | |
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| 25 | // =====[ component_Meta_Predictor_Glue ]============================= |
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| 26 | |
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| 27 | list_port_map.clear(); |
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| 28 | log_printf(INFO,Meta_Predictor,"vhdl_body","Instanciation : component_Meta_Predictor_Glue"); |
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| 29 | |
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| 30 | // Instantiation |
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| 31 | |
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| 32 | // Interface Predict |
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| 33 | for (uint32_t i=0; i<_param._nb_prediction; i++) |
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| 34 | { |
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| 35 | if (_param._have_meta_predictor) |
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| 36 | { |
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| 37 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_PREDICTOR_0_ACK_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_0_ACK_"+toString(i)); |
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| 38 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_PREDICTOR_1_ACK_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_1_ACK_"+toString(i)); |
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| 39 | } |
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| 40 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_PREDICTOR_2_ACK_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_2_ACK_"+toString(i)); |
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| 41 | vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_ACK_"+toString(i)+" ", " out_PREDICT_ACK_"+toString(i)); |
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| 42 | if (_param._have_meta_predictor) |
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| 43 | { |
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| 44 | if (_param._predictor_0_have_bht) |
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| 45 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_PREDICTOR_0_BHT_HISTORY_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_0_BHT_HISTORY_"+toString(i)); |
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| 46 | if (_param._predictor_0_have_pht) |
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| 47 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_PREDICTOR_0_PHT_HISTORY_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_0_PHT_HISTORY_"+toString(i)); |
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| 48 | if (_param._predictor_1_have_bht) |
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| 49 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_PREDICTOR_1_BHT_HISTORY_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_1_BHT_HISTORY_"+toString(i)); |
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| 50 | if (_param._predictor_1_have_pht) |
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| 51 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_PREDICTOR_1_PHT_HISTORY_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_1_PHT_HISTORY_"+toString(i)); |
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| 52 | } |
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| 53 | if (_param._predictor_2_have_bht) |
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| 54 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_PREDICTOR_2_BHT_HISTORY_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_2_BHT_HISTORY_"+toString(i)); |
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| 55 | if (_param._predictor_2_have_pht) |
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| 56 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_PREDICTOR_2_PHT_HISTORY_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_2_PHT_HISTORY_"+toString(i)); |
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| 57 | vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_HISTORY_"+toString(i)+" ", " out_PREDICT_HISTORY_"+toString(i)); |
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| 58 | vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_DIRECTION_"+toString(i)+" ", " out_PREDICT_DIRECTION_"+toString(i)); |
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| 59 | } |
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| 60 | |
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| 61 | // Interface Branch_complete |
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| 62 | |
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| 63 | for (uint32_t i=0; i<_param._nb_branch_complete; i++) |
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| 64 | { |
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| 65 | if (_param._have_meta_predictor) |
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| 66 | { |
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| 67 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", " in_BRANCH_COMPLETE_VAL_"+toString(i)); |
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| 68 | vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_PREDICTOR_2_VAL_"+toString(i)+" ", "signal_BRANCH_COMPLETE_PREDICTOR_2_VAL_"+toString(i)); |
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| 69 | |
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| 70 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_PREDICTOR_0_ACK_"+toString(i)+" ", "signal_BRANCH_COMPLETE_PREDICTOR_0_ACK_"+toString(i)); |
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| 71 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_PREDICTOR_1_ACK_"+toString(i)+" ", "signal_BRANCH_COMPLETE_PREDICTOR_1_ACK_"+toString(i)); |
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| 72 | } |
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| 73 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_PREDICTOR_2_ACK_"+toString(i)+" ", "signal_BRANCH_COMPLETE_PREDICTOR_2_ACK_"+toString(i)); |
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| 74 | vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_ACK_"+toString(i)+" ", " out_BRANCH_COMPLETE_ACK_"+toString(i)); |
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| 75 | |
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| 76 | if (_param._have_meta_predictor) |
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| 77 | { |
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| 78 | if (_param._predictor_0_have_bht) |
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| 79 | vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY_"+toString(i)+"", "signal_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY_"+toString(i)); |
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| 80 | if (_param._predictor_0_have_pht) |
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| 81 | vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY_"+toString(i)+"", "signal_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY_"+toString(i)); |
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| 82 | if (_param._predictor_1_have_bht) |
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| 83 | vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY_"+toString(i)+"", "signal_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY_"+toString(i)); |
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| 84 | if (_param._predictor_1_have_pht) |
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| 85 | vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY_"+toString(i)+"", "signal_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY_"+toString(i)); |
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| 86 | } |
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| 87 | if (_param._predictor_2_have_bht) |
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| 88 | vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY_"+toString(i)+"", "signal_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY_"+toString(i)); |
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| 89 | if (_param._predictor_2_have_pht) |
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| 90 | vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY_"+toString(i)+"", "signal_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY_"+toString(i)); |
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| 91 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_HISTORY_"+toString(i)+" ", " in_BRANCH_COMPLETE_HISTORY_"+toString(i)); |
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| 92 | if (_param._have_meta_predictor) |
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| 93 | { |
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| 94 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+" ", " in_BRANCH_COMPLETE_DIRECTION_"+toString(i)); |
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| 95 | vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION_"+toString(i)+" ", "signal_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION_"+toString(i)); |
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| 96 | } |
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| 97 | } |
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| 98 | |
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| 99 | vhdl.set_body_component ("component_Meta_Predictor_Glue",_name+"_Meta_Predictor_Glue",list_port_map); |
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| 100 | |
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| 101 | // =====[ component_Two_Level_Branch_Predictor_2 ]==================== |
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| 102 | |
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| 103 | list_port_map.clear(); |
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| 104 | log_printf(INFO,Meta_Predictor,"vhdl_body","Instanciation : component_Two_Level_Branch_Predictor_2"); |
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| 105 | |
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| 106 | // Instantiation |
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[15] | 107 | vhdl.set_body_component_port_map (list_port_map,"in_CLOCK ","in_CLOCK "); |
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| 108 | vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); |
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[5] | 109 | |
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| 110 | for (uint32_t i=0; i<_param._nb_prediction; i++) |
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| 111 | { |
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| 112 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_VAL_"+toString(i)+" ", " in_PREDICT_VAL_"+toString(i)); |
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| 113 | vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_ACK_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_2_ACK_"+toString(i)); |
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| 114 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_ADDRESS_"+toString(i)+" ", " in_PREDICT_ADDRESS_"+toString(i)); |
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| 115 | if (_param._predictor_2_have_bht) |
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| 116 | vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_BHT_HISTORY_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_2_BHT_HISTORY_"+toString(i)); |
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| 117 | if (_param._predictor_2_have_pht) |
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| 118 | vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_PHT_HISTORY_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_2_PHT_HISTORY_"+toString(i)); |
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| 119 | } |
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| 120 | |
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| 121 | for (uint32_t i=0; i<_param._nb_branch_complete; i++) |
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| 122 | { |
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| 123 | if (_param._have_meta_predictor) |
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| 124 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", "signal_BRANCH_COMPLETE_PREDICTOR_2_VAL_"+toString(i)); |
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| 125 | else |
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| 126 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", " in_BRANCH_COMPLETE_VAL_"+toString(i)); |
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| 127 | vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_ACK_"+toString(i)+" ", "signal_BRANCH_COMPLETE_PREDICTOR_2_ACK_"+toString(i)); |
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| 128 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+" ", " in_BRANCH_COMPLETE_ADDRESS_"+toString(i)); |
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| 129 | if (_param._predictor_2_have_bht) |
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| 130 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i)+"", "signal_BRANCH_COMPLETE_PREDICTOR_2_BHT_HISTORY_"+toString(i)); |
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| 131 | if (_param._predictor_2_have_pht) |
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| 132 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_PHT_HISTORY_"+toString(i)+"", "signal_BRANCH_COMPLETE_PREDICTOR_2_PHT_HISTORY_"+toString(i)); |
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| 133 | if (_param._have_meta_predictor) |
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| 134 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+" ", "signal_BRANCH_COMPLETE_PREDICTOR_2_DIRECTION_"+toString(i)); |
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| 135 | else |
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| 136 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+" ", " in_BRANCH_COMPLETE_DIRECTION_"+toString(i)); |
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| 137 | } |
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| 138 | |
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| 139 | vhdl.set_body_component ("component_Two_Level_Branch_Predictor_2",_name+"_Two_Level_Branch_Predictor_2",list_port_map); |
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| 140 | |
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| 141 | if (_param._have_meta_predictor) |
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| 142 | { |
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| 143 | // =====[ component_Two_Level_Branch_Predictor_1 ]==================== |
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| 144 | |
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| 145 | list_port_map.clear(); |
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| 146 | log_printf(INFO,Meta_Predictor,"vhdl_body","Instanciation : component_Two_Level_Branch_Predictor_1"); |
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| 147 | |
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| 148 | // Instantiation |
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[15] | 149 | vhdl.set_body_component_port_map (list_port_map,"in_CLOCK ","in_CLOCK "); |
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| 150 | vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); |
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[5] | 151 | |
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| 152 | for (uint32_t i=0; i<_param._nb_prediction; i++) |
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| 153 | { |
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| 154 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_VAL_"+toString(i)+" ", " in_PREDICT_VAL_"+toString(i)); |
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| 155 | vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_ACK_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_1_ACK_"+toString(i)); |
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| 156 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_ADDRESS_"+toString(i)+" ", " in_PREDICT_ADDRESS_"+toString(i)); |
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| 157 | if (_param._predictor_1_have_bht) |
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| 158 | vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_BHT_HISTORY_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_1_BHT_HISTORY_"+toString(i)); |
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| 159 | if (_param._predictor_1_have_pht) |
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| 160 | vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_PHT_HISTORY_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_1_PHT_HISTORY_"+toString(i)); |
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| 161 | } |
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| 162 | |
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| 163 | for (uint32_t i=0; i<_param._nb_branch_complete; i++) |
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| 164 | { |
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| 165 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", " in_BRANCH_COMPLETE_VAL_"+toString(i)); |
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| 166 | vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_ACK_"+toString(i)+" ", "signal_BRANCH_COMPLETE_PREDICTOR_1_ACK_"+toString(i)); |
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| 167 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+" ", " in_BRANCH_COMPLETE_ADDRESS_"+toString(i)); |
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| 168 | if (_param._predictor_1_have_bht) |
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| 169 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i)+"", "signal_BRANCH_COMPLETE_PREDICTOR_1_BHT_HISTORY_"+toString(i)); |
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| 170 | if (_param._predictor_1_have_pht) |
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| 171 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_PHT_HISTORY_"+toString(i)+"", "signal_BRANCH_COMPLETE_PREDICTOR_1_PHT_HISTORY_"+toString(i)); |
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| 172 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+" ", " in_BRANCH_COMPLETE_DIRECTION_"+toString(i)); |
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| 173 | } |
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| 174 | |
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| 175 | vhdl.set_body_component ("component_Two_Level_Branch_Predictor_1",_name+"_Two_Level_Branch_Predictor_1",list_port_map); |
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| 176 | |
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| 177 | // =====[ component_Two_Level_Branch_Predictor_0 ]==================== |
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| 178 | |
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| 179 | list_port_map.clear(); |
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| 180 | log_printf(INFO,Meta_Predictor,"vhdl_body","Instanciation : component_Two_Level_Branch_Predictor_0"); |
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| 181 | |
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| 182 | // Instantiation |
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[15] | 183 | vhdl.set_body_component_port_map (list_port_map,"in_CLOCK ","in_CLOCK "); |
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| 184 | vhdl.set_body_component_port_map (list_port_map,"in_NRESET","in_NRESET"); |
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[5] | 185 | |
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| 186 | for (uint32_t i=0; i<_param._nb_prediction; i++) |
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| 187 | { |
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| 188 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_VAL_"+toString(i)+" ", " in_PREDICT_VAL_"+toString(i)); |
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| 189 | vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_ACK_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_0_ACK_"+toString(i)); |
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| 190 | vhdl.set_body_component_port_map (list_port_map," in_PREDICT_ADDRESS_"+toString(i)+" ", " in_PREDICT_ADDRESS_"+toString(i)); |
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| 191 | if (_param._predictor_0_have_bht) |
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| 192 | vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_BHT_HISTORY_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_0_BHT_HISTORY_"+toString(i)); |
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| 193 | if (_param._predictor_0_have_pht) |
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| 194 | vhdl.set_body_component_port_map (list_port_map,"out_PREDICT_PHT_HISTORY_"+toString(i)+" ", "signal_PREDICT_PREDICTOR_0_PHT_HISTORY_"+toString(i)); |
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| 195 | } |
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| 196 | |
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| 197 | for (uint32_t i=0; i<_param._nb_branch_complete; i++) |
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| 198 | { |
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| 199 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_VAL_"+toString(i)+" ", " in_BRANCH_COMPLETE_VAL_"+toString(i)); |
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| 200 | vhdl.set_body_component_port_map (list_port_map,"out_BRANCH_COMPLETE_ACK_"+toString(i)+" ", "signal_BRANCH_COMPLETE_PREDICTOR_0_ACK_"+toString(i)); |
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| 201 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_ADDRESS_"+toString(i)+" ", " in_BRANCH_COMPLETE_ADDRESS_"+toString(i)); |
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| 202 | if (_param._predictor_0_have_bht) |
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| 203 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_BHT_HISTORY_"+toString(i)+"", "signal_BRANCH_COMPLETE_PREDICTOR_0_BHT_HISTORY_"+toString(i)); |
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| 204 | if (_param._predictor_0_have_pht) |
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| 205 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_PHT_HISTORY_"+toString(i)+"", "signal_BRANCH_COMPLETE_PREDICTOR_0_PHT_HISTORY_"+toString(i)); |
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| 206 | vhdl.set_body_component_port_map (list_port_map," in_BRANCH_COMPLETE_DIRECTION_"+toString(i)+" ", " in_BRANCH_COMPLETE_DIRECTION_"+toString(i)); |
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| 207 | } |
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| 208 | |
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| 209 | vhdl.set_body_component ("component_Two_Level_Branch_Predictor_0",_name+"_Two_Level_Branch_Predictor_0",list_port_map); |
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| 210 | } |
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| 211 | |
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| 212 | log_printf(FUNC,Meta_Predictor,"vhdl_body","End"); |
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| 213 | }; |
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| 214 | |
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| 215 | }; // end namespace meta_predictor |
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| 216 | }; // end namespace predictor |
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| 217 | }; // end namespace stage_1_ifetch |
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| 218 | |
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| 219 | }; // end namespace behavioural |
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| 220 | }; // end namespace morpheo |
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| 221 | #endif |
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