| [59] | 1 | #ifndef morpheo_behavioural_Constants_h |
|---|
| 2 | #define morpheo_behavioural_Constants_h |
|---|
| 3 | |
|---|
| 4 | namespace morpheo { |
|---|
| 5 | namespace behavioural { |
|---|
| 6 | |
|---|
| 7 | //=========================================================[ Type ]===== |
|---|
| 8 | #define TYPE_MEMORY 0x1 // 00001 |
|---|
| 9 | |
|---|
| 10 | //====================================================[ Operation ]===== |
|---|
| 11 | |
|---|
| 12 | //-------------------------------------------------------[ Memory ]----- |
|---|
| [71] | 13 | #define OPERATION_MEMORY_LOAD 0x0 // 000_0000 |
|---|
| [59] | 14 | #define OPERATION_MEMORY_LOAD_8_Z 0x0 // 000_0000 |
|---|
| 15 | #define OPERATION_MEMORY_LOAD_16_Z 0x20 // 010_0000 |
|---|
| 16 | #define OPERATION_MEMORY_LOAD_32_Z 0x40 // 100_0000 |
|---|
| 17 | #define OPERATION_MEMORY_LOAD_64_Z 0x60 // 110_0000 |
|---|
| 18 | #define OPERATION_MEMORY_LOAD_8_S 0x10 // 001_0000 |
|---|
| 19 | #define OPERATION_MEMORY_LOAD_16_S 0x30 // 011_0000 |
|---|
| 20 | #define OPERATION_MEMORY_LOAD_32_S 0x50 // 101_0000 |
|---|
| 21 | #define OPERATION_MEMORY_LOAD_64_S 0x70 // 111_0000 |
|---|
| 22 | |
|---|
| 23 | #define OPERATION_MEMORY_STORE_8 0x8 // 000_1000 |
|---|
| 24 | #define OPERATION_MEMORY_STORE_16 0x9 // 000_1001 |
|---|
| 25 | #define OPERATION_MEMORY_STORE_32 0xa // 000_1010 |
|---|
| 26 | #define OPERATION_MEMORY_STORE_64 0xb // 000_1011 |
|---|
| 27 | #define OPERATION_MEMORY_STORE_HEAD_OK 0xc // 000_1100 |
|---|
| 28 | #define OPERATION_MEMORY_STORE_HEAD_KO 0xd // 000_1101 |
|---|
| 29 | |
|---|
| 30 | #define OPERATION_MEMORY_LOCK 0x1 // 000_0001 |
|---|
| 31 | #define OPERATION_MEMORY_INVALIDATE 0x2 // 000_0010 |
|---|
| 32 | #define OPERATION_MEMORY_PREFETCH 0x3 // 000_0011 |
|---|
| 33 | #define OPERATION_MEMORY_FLUSH 0x6 // 000_0110 |
|---|
| 34 | #define OPERATION_MEMORY_SYNCHRONIZATION 0x7 // 000_0111 |
|---|
| 35 | |
|---|
| 36 | #define is_operation_memory_load(x) \ |
|---|
| 37 | ((x == OPERATION_MEMORY_LOAD_8_Z ) or \ |
|---|
| 38 | (x == OPERATION_MEMORY_LOAD_16_Z) or \ |
|---|
| 39 | (x == OPERATION_MEMORY_LOAD_32_Z) or \ |
|---|
| 40 | (x == OPERATION_MEMORY_LOAD_64_Z) or \ |
|---|
| 41 | (x == OPERATION_MEMORY_LOAD_8_S ) or \ |
|---|
| 42 | (x == OPERATION_MEMORY_LOAD_16_S) or \ |
|---|
| 43 | (x == OPERATION_MEMORY_LOAD_32_S) or \ |
|---|
| 44 | (x == OPERATION_MEMORY_LOAD_64_S) ) |
|---|
| 45 | |
|---|
| 46 | #define is_operation_memory_store(x) \ |
|---|
| 47 | ((x == OPERATION_MEMORY_STORE_8 ) or \ |
|---|
| 48 | (x == OPERATION_MEMORY_STORE_16 ) or \ |
|---|
| 49 | (x == OPERATION_MEMORY_STORE_32 ) or \ |
|---|
| 50 | (x == OPERATION_MEMORY_STORE_64 ) or \ |
|---|
| 51 | (x == OPERATION_MEMORY_STORE_HEAD_OK) or \ |
|---|
| 52 | (x == OPERATION_MEMORY_STORE_HEAD_KO)) |
|---|
| 53 | |
|---|
| 54 | #define is_operation_memory_store_head(x) \ |
|---|
| 55 | ((x == OPERATION_MEMORY_STORE_HEAD_OK) or \ |
|---|
| 56 | (x == OPERATION_MEMORY_STORE_HEAD_KO)) |
|---|
| 57 | |
|---|
| [71] | 58 | #define is_operation_memory_load_signed(x) \ |
|---|
| 59 | ((x == OPERATION_MEMORY_LOAD_8_S ) or \ |
|---|
| 60 | (x == OPERATION_MEMORY_LOAD_16_S) or \ |
|---|
| 61 | (x == OPERATION_MEMORY_LOAD_32_S) or \ |
|---|
| 62 | (x == OPERATION_MEMORY_LOAD_64_S) ) |
|---|
| 63 | |
|---|
| [59] | 64 | #define MEMORY_ACCESS_8 0x0 |
|---|
| 65 | #define MEMORY_ACCESS_16 0x1 |
|---|
| 66 | #define MEMORY_ACCESS_32 0x2 |
|---|
| 67 | #define MEMORY_ACCESS_64 0x3 |
|---|
| 68 | |
|---|
| [71] | 69 | #define MEMORY_SIZE_8 8 |
|---|
| 70 | #define MEMORY_SIZE_16 16 |
|---|
| 71 | #define MEMORY_SIZE_32 32 |
|---|
| 72 | #define MEMORY_SIZE_64 64 |
|---|
| 73 | |
|---|
| [59] | 74 | #define MASK_MEMORY_ACCESS_8 0x0 |
|---|
| 75 | #define MASK_MEMORY_ACCESS_16 0x1 |
|---|
| 76 | #define MASK_MEMORY_ACCESS_32 0x3 |
|---|
| 77 | #define MASK_MEMORY_ACCESS_64 0x7 |
|---|
| 78 | |
|---|
| [71] | 79 | #define memory_size(x) \ |
|---|
| 80 | (((x==OPERATION_MEMORY_LOAD_16_Z)or \ |
|---|
| 81 | (x==OPERATION_MEMORY_LOAD_16_S)or \ |
|---|
| 82 | (x==OPERATION_MEMORY_STORE_16 ))?MEMORY_SIZE_16: \ |
|---|
| 83 | (((x==OPERATION_MEMORY_LOAD_32_Z)or \ |
|---|
| 84 | (x==OPERATION_MEMORY_LOAD_32_S)or \ |
|---|
| 85 | (x==OPERATION_MEMORY_STORE_32 ))?MEMORY_SIZE_32: \ |
|---|
| 86 | (((x==OPERATION_MEMORY_LOAD_64_Z)or \ |
|---|
| 87 | (x==OPERATION_MEMORY_LOAD_64_S)or \ |
|---|
| 88 | (x==OPERATION_MEMORY_STORE_64 ))?MEMORY_SIZE_64:MEMORY_SIZE_8))) |
|---|
| 89 | |
|---|
| [59] | 90 | #define memory_access(x) \ |
|---|
| 91 | (((x==OPERATION_MEMORY_LOAD_16_Z)or \ |
|---|
| 92 | (x==OPERATION_MEMORY_LOAD_16_S)or \ |
|---|
| 93 | (x==OPERATION_MEMORY_STORE_16 ))?MEMORY_ACCESS_16: \ |
|---|
| 94 | (((x==OPERATION_MEMORY_LOAD_32_Z)or \ |
|---|
| 95 | (x==OPERATION_MEMORY_LOAD_32_S)or \ |
|---|
| 96 | (x==OPERATION_MEMORY_STORE_32 ))?MEMORY_ACCESS_32: \ |
|---|
| 97 | (((x==OPERATION_MEMORY_LOAD_64_Z)or \ |
|---|
| 98 | (x==OPERATION_MEMORY_LOAD_64_S)or \ |
|---|
| 99 | (x==OPERATION_MEMORY_STORE_64 ))?MEMORY_ACCESS_64:MEMORY_ACCESS_8))) |
|---|
| 100 | |
|---|
| 101 | #define mask_memory_access(x) \ |
|---|
| 102 | (((x==OPERATION_MEMORY_LOAD_16_Z)or \ |
|---|
| 103 | (x==OPERATION_MEMORY_LOAD_16_S)or \ |
|---|
| 104 | (x==OPERATION_MEMORY_STORE_16 ))?MASK_MEMORY_ACCESS_16: \ |
|---|
| 105 | (((x==OPERATION_MEMORY_LOAD_32_Z)or \ |
|---|
| 106 | (x==OPERATION_MEMORY_LOAD_32_S)or \ |
|---|
| 107 | (x==OPERATION_MEMORY_STORE_32 ))?MASK_MEMORY_ACCESS_32: \ |
|---|
| 108 | (((x==OPERATION_MEMORY_LOAD_64_Z)or \ |
|---|
| 109 | (x==OPERATION_MEMORY_LOAD_64_S)or \ |
|---|
| 110 | (x==OPERATION_MEMORY_STORE_64 ))?MASK_MEMORY_ACCESS_64:MASK_MEMORY_ACCESS_8))) |
|---|
| 111 | |
|---|
| 112 | //====================================================[ Exception ]===== |
|---|
| 113 | // Exception - OpenRISC |
|---|
| 114 | |
|---|
| 115 | #define EXCEPTION_NONE 0x00 // none exception |
|---|
| 116 | #define EXCEPTION_RESET 0x01 // software or hardware reset |
|---|
| 117 | #define EXCEPTION_BUS_ERROR 0x02 // Access at a invalid physical adress |
|---|
| 118 | #define EXCEPTION_DATA_PAGE 0x03 // No matching or page violation protection in pages tables |
|---|
| 119 | #define EXCEPTION_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables |
|---|
| 120 | #define EXCEPTION_TICK_TIMER 0x05 // Tick timer interruption |
|---|
| 121 | #define EXCEPTION_ALIGNMENT 0x06 // Load/Store access is not aligned |
|---|
| 122 | #define EXCEPTION_ILLEGAL_INSTRUCTION 0x07 // Instruction is illegal (no implemented) |
|---|
| 123 | #define EXCEPTION_INTERRUPT 0x08 // External interruption |
|---|
| 124 | #define EXCEPTION_DATA_TLB 0x09 // DTLB miss |
|---|
| 125 | #define EXCEPTION_INSTRUCTION_TLB 0x0a // ITLB miss |
|---|
| 126 | #define EXCEPTION_RANGE 0x0b // Overflow or access at a unimplemented register or context |
|---|
| 127 | #define EXCEPTION_SYSCALL 0x0c // System Call |
|---|
| 128 | #define EXCEPTION_FLOATING_POINT 0x0d // Caused by a floating instruction |
|---|
| 129 | #define EXCEPTION_TRAP 0x0e // L.trap or debug unit |
|---|
| 130 | #define EXCEPTION_RESERVED_0 0x0f // Reserved for a futur usage |
|---|
| 131 | #define EXCEPTION_RESERVED_1 0x10 // Reserved for a futur usage |
|---|
| 132 | #define EXCEPTION_RESERVED_2 0x11 // Reserved for a futur usage |
|---|
| 133 | #define EXCEPTION_RESERVED_3 0x12 // Reserved for a futur usage |
|---|
| 134 | #define EXCEPTION_RESERVED_4 0x13 // Reserved for a futur usage |
|---|
| 135 | #define EXCEPTION_RESERVED_5 0x14 // Reserved for a futur usage |
|---|
| 136 | #define EXCEPTION_RESERVED_6 0x15 // Reserved for implemented specific exceptions |
|---|
| 137 | #define EXCEPTION_RESERVED_7 0x16 // Reserved for implemented specific exceptions |
|---|
| 138 | #define EXCEPTION_RESERVED_8 0x17 // Reserved for implemented specific exceptions |
|---|
| 139 | #define EXCEPTION_RESERVED_9 0x18 // Reserved for implemented specific exceptions |
|---|
| 140 | #define EXCEPTION_CUSTOM_0 0x19 // Reserved for custom exceptions |
|---|
| 141 | #define EXCEPTION_CUSTOM_1 0x1a // Reserved for custom exceptions |
|---|
| 142 | #define EXCEPTION_CUSTOM_2 0x1b // Reserved for custom exceptions |
|---|
| 143 | #define EXCEPTION_CUSTOM_3 0x1c // Reserved for custom exceptions |
|---|
| 144 | #define EXCEPTION_CUSTOM_4 0x1d // Reserved for custom exceptions |
|---|
| 145 | #define EXCEPTION_CUSTOM_5 0x1e // Reserved for custom exceptions |
|---|
| 146 | #define EXCEPTION_CUSTOM_6 0x1f // Reserved for custom exceptions |
|---|
| 147 | |
|---|
| 148 | // Exception Execution |
|---|
| 149 | #define EXCEPTION_MEMORY_NONE 0x0 // Load/Store access is not aligned |
|---|
| 150 | #define EXCEPTION_MEMORY_ALIGNMENT 0x1 // Load/Store access is not aligned |
|---|
| 151 | #define EXCEPTION_MEMORY_DATA_TLB 0x2 // DTLB miss |
|---|
| 152 | #define EXCEPTION_MEMORY_DATA_PAGE 0x3 // No matching or page violation protection in pages tables |
|---|
| 153 | #define EXCEPTION_MEMORY_BUS_ERROR 0x4 // Access at a invalid physical address |
|---|
| 154 | #define EXCEPTION_MEMORY_MISS_SPECULATION 0x5 // Load miss speculation |
|---|
| [71] | 155 | #define EXCEPTION_MEMORY_LOAD_SPECULATIVE 0x6 // The load is speculative : write in register file, but don't commit |
|---|
| [59] | 156 | |
|---|
| [62] | 157 | //==================================================[ dcache_type ]===== |
|---|
| [71] | 158 | # define DCACHE_LOAD 0x0 // 0000 |
|---|
| 159 | # define DCACHE_LOCK 0x1 // 0001 |
|---|
| 160 | # define DCACHE_INVALIDATE 0x2 // 0010 |
|---|
| 161 | # define DCACHE_PREFETCH 0x3 // 0011 |
|---|
| 162 | //#define DCACHE_ 0x4 // 0100 |
|---|
| 163 | //#define DCACHE_ 0x5 // 0101 |
|---|
| 164 | # define DCACHE_FLUSH 0x6 // 0110 |
|---|
| 165 | # define DCACHE_SYNCHRONIZATION 0x7 // 0111 |
|---|
| 166 | # define DCACHE_STORE_8 0x8 // 1000 |
|---|
| 167 | # define DCACHE_STORE_16 0x9 // 1001 |
|---|
| 168 | # define DCACHE_STORE_32 0xa // 1010 |
|---|
| 169 | # define DCACHE_STORE_64 0xb // 1011 |
|---|
| 170 | //#define DCACHE_ 0xc // 1100 |
|---|
| 171 | //#define DCACHE_ 0xd // 1101 |
|---|
| 172 | //#define DCACHE_ 0xe // 1110 |
|---|
| 173 | //#define DCACHE_ 0xf // 1111 |
|---|
| [62] | 174 | |
|---|
| 175 | |
|---|
| 176 | // just take the 4 less significative bits. |
|---|
| 177 | #define operation_to_dcache_type(x) (x&0xf) |
|---|
| 178 | |
|---|
| [59] | 179 | /* |
|---|
| 180 | #define _size_instruction 32 |
|---|
| 181 | #define _size_instruction_log2 5 |
|---|
| 182 | |
|---|
| 183 | //----------------------------------------------------[ Operation ]----- |
|---|
| 184 | // #define _nb_operation 32 |
|---|
| 185 | // #define _size_operation 5 |
|---|
| 186 | |
|---|
| 187 | #define _operation_none 0x0 |
|---|
| 188 | #define _operation_l_adds 0x1 |
|---|
| 189 | #define _operation_l_addu 0x2 |
|---|
| 190 | #define _operation_l_subs 0x3 |
|---|
| 191 | #define _operation_l_and 0x4 |
|---|
| 192 | #define _operation_l_or 0x5 |
|---|
| 193 | #define _operation_l_xor 0x6 |
|---|
| 194 | #define _operation_l_cmove 0x7 |
|---|
| 195 | #define _operation_l_read_imm 0x8 |
|---|
| 196 | #define _operation_l_movhi 0x9 |
|---|
| 197 | #define _operation_l_muls 0xa |
|---|
| 198 | #define _operation_l_mulu 0xb |
|---|
| 199 | #define _operation_l_divs 0xc |
|---|
| 200 | #define _operation_l_divu 0xd |
|---|
| 201 | #define _operation_l_exts 0xe |
|---|
| 202 | #define _operation_l_extz 0xf |
|---|
| 203 | #define _operation_l_ff1 0x10 |
|---|
| 204 | #define _operation_l_fl1 0x11 |
|---|
| 205 | #define _operation_l_sll 0x12 |
|---|
| 206 | #define _operation_l_sla 0x13 |
|---|
| 207 | #define _operation_l_srl 0x14 |
|---|
| 208 | #define _operation_l_ror 0x15 |
|---|
| 209 | #define _operation_l_cmp_eq 0x16 |
|---|
| 210 | #define _operation_l_cmp_ne 0x17 |
|---|
| 211 | #define _operation_l_cmp_ges 0x18 |
|---|
| 212 | #define _operation_l_cmp_geu 0x19 |
|---|
| 213 | #define _operation_l_cmp_gts 0x1a |
|---|
| 214 | #define _operation_l_cmp_gtu 0x1b |
|---|
| 215 | #define _operation_l_cmp_les 0x1c |
|---|
| 216 | #define _operation_l_cmp_leu 0x1d |
|---|
| 217 | #define _operation_l_cmp_lts 0x1e |
|---|
| 218 | #define _operation_l_cmp_ltu 0x1f |
|---|
| 219 | |
|---|
| 220 | //--------------------------------------------------[ destination ]----- |
|---|
| 221 | #define _size_destination1 4 |
|---|
| 222 | |
|---|
| 223 | #define cst_DESTINATION1_NONE 0x0 |
|---|
| 224 | #define mask_DESTINATION1_GPR 0x1 |
|---|
| 225 | #define mask_DESTINATION1_MEMORY 0x2 |
|---|
| 226 | #define mask_DESTINATION1_SPR 0x4 |
|---|
| 227 | #define mask_DESTINATION1_MAC_UNIT 0x8 |
|---|
| 228 | |
|---|
| 229 | #define _size_destination2 3 |
|---|
| 230 | |
|---|
| 231 | #define cst_DESTINATION2_NONE 0x0 |
|---|
| 232 | #define mask_DESTINATION2_COMMIT 0x1 |
|---|
| 233 | #define mask_DESTINATION2_MEMORY 0x2 |
|---|
| 234 | #define mask_DESTINATION2_SPR 0x4 |
|---|
| 235 | |
|---|
| 236 | //----------------------------------------------------[ exec_flag ]----- |
|---|
| 237 | #define _size_exec_flag 2 |
|---|
| 238 | |
|---|
| 239 | #define mask_EXEC_FLAG_NONE 0x1 |
|---|
| 240 | #define mask_EXEC_FLAG_CARRY 0x1 |
|---|
| 241 | #define mask_EXEC_FLAG_FLAG 0x1 |
|---|
| 242 | #define mask_EXEC_FLAG_OVERFLOW 0x2 |
|---|
| 243 | |
|---|
| 244 | //---------------------------------------------------[ exec_excep ]----- |
|---|
| 245 | #define _size_exec_excep 1 |
|---|
| 246 | |
|---|
| 247 | #define mask_EXEC_EXCEP_NONE 0x0 |
|---|
| 248 | #define mask_EXEC_EXCEP_RANGE 0x1 |
|---|
| 249 | |
|---|
| 250 | //----------------------------------------------------[ Condition ]----- |
|---|
| 251 | #define _size_condition 3 |
|---|
| 252 | |
|---|
| 253 | #define cst_CONDITION_UNCONDITIONAL 0x0 // None condition (jump) |
|---|
| 254 | #define mask_CONDITION_CONDITIONAL 0x2 |
|---|
| 255 | #define mask_CONDITION_CONDITIONAL_NF 0x0 // Branch if Flag is clear |
|---|
| 256 | #define mask_CONDITION_CONDITIONAL_F 0x1 // Branch if Flag is set |
|---|
| 257 | #define mask_CONDITION_REG 0x4 // Branch if a register is read |
|---|
| 258 | #define mask_CONDITION_STACK 0x8 // Branch with pop in stack pointer |
|---|
| 259 | |
|---|
| 260 | //-------------------------------------------------[ branch_state ]----- |
|---|
| 261 | #define cst_BRANCH_STATE_NONE 0x0 // 0 0 |
|---|
| 262 | #define cst_BRANCH_STATE_NSPEC_TAKE 0x1 // 0 1 -> incondionnal |
|---|
| 263 | #define cst_BRANCH_STATE_SPEC_NTAKE 0x2 // 1 0 |
|---|
| 264 | #define cst_BRANCH_STATE_SPEC_TAKE 0x3 // 1 1 |
|---|
| 265 | */ |
|---|
| 266 | |
|---|
| 267 | /* |
|---|
| 268 | #define M_CPU_SIZE_INST 32 |
|---|
| 269 | |
|---|
| 270 | //---------------------------------------------------- |
|---|
| 271 | // Exception type |
|---|
| 272 | //---------------------------------------------------- |
|---|
| 273 | |
|---|
| 274 | #define M_CPU_LOG2_NB_EXCP 5 |
|---|
| 275 | #define M_CPU_NB_EXCP 32 |
|---|
| 276 | |
|---|
| 277 | #define EXCP_NO 0x00 // none exception |
|---|
| 278 | #define EXCP_RESET 0x01 // software or hardware reset |
|---|
| 279 | #define EXCP_BERR 0x02 // Access at a invalid physical adress |
|---|
| 280 | #define EXCP_D_PAGE 0x03 // No matching or page violation protection in pages tables |
|---|
| 281 | #define EXCP_I_PAGE 0x04 // No matching or page violation protection in pages tables |
|---|
| 282 | #define EXCP_TICK_TIMER 0x05 // Tick timer interruption |
|---|
| 283 | #define EXCP_ALIGNMENT 0x06 // Load/Store access is not aligned |
|---|
| 284 | #define EXCP_ILL_INST 0x07 // Instruction is illegal (no implemented) |
|---|
| 285 | #define EXCP_IRQ 0x08 // External interruption |
|---|
| 286 | #define EXCP_D_TLB 0x09 // DTLB miss |
|---|
| 287 | #define EXCP_I_TLB 0x0a // ITLB miss |
|---|
| 288 | #define EXCP_RANGE 0x0b // Overflow or access at a unimplemented register or context |
|---|
| 289 | #define EXCP_SYSCALL 0x0c // System Call |
|---|
| 290 | #define EXCP_FP 0x0d // Caused by a floating instruction |
|---|
| 291 | #define EXCP_TRAP 0x0e // L.trap or debug unit |
|---|
| 292 | #define EXCP_RES0 0x0f // Reserved for a futur usage |
|---|
| 293 | #define EXCP_RES1 0x10 // Reserved for a futur usage |
|---|
| 294 | #define EXCP_RES2 0x11 // Reserved for a futur usage |
|---|
| 295 | #define EXCP_RES3 0x12 // Reserved for a futur usage |
|---|
| 296 | #define EXCP_RES4 0x13 // Reserved for a futur usage |
|---|
| 297 | #define EXCP_RES5 0x14 // Reserved for a futur usage |
|---|
| 298 | #define EXCP_RES6 0x15 // Reserved for implemented specific exceptions |
|---|
| 299 | #define EXCP_RES7 0x16 // Reserved for implemented specific exceptions |
|---|
| 300 | #define EXCP_RES8 0x17 // Reserved for implemented specific exceptions |
|---|
| 301 | #define EXCP_RES9 0x18 // Reserved for implemented specific exceptions |
|---|
| 302 | #define EXCP_CUST0 0x19 // Reserved for custom exceptions |
|---|
| 303 | #define EXCP_CUST1 0x1a // Reserved for custom exceptions |
|---|
| 304 | #define EXCP_CUST2 0x1b // Reserved for custom exceptions |
|---|
| 305 | #define EXCP_CUST3 0x1c // Reserved for custom exceptions |
|---|
| 306 | #define EXCP_CUST4 0x1d // Reserved for custom exceptions |
|---|
| 307 | #define EXCP_CUST5 0x1e // Reserved for custom exceptions |
|---|
| 308 | #define EXCP_CUST6 0x1f // Reserved for custom exceptions |
|---|
| 309 | |
|---|
| 310 | //---------------------------------------------------- |
|---|
| 311 | // Flags |
|---|
| 312 | //---------------------------------------------------- |
|---|
| 313 | |
|---|
| 314 | #define M_CPU_NB_FLAG 3 |
|---|
| 315 | |
|---|
| 316 | // Integer flags |
|---|
| 317 | #define FLAG_F 0x1 // Conditionnal branch flag |
|---|
| 318 | #define FLAG_CY 0x2 // Carry was produced by last arithmétic operation |
|---|
| 319 | #define FLAG_OV 0x4 // Overflow occured during last arithmetic operation |
|---|
| 320 | |
|---|
| 321 | // Floating flags |
|---|
| 322 | #define FLAG_OVF 0x004 // Overflow occured during last arithmetic operation |
|---|
| 323 | #define FLAG_UNF 0x008 // Underflow flags |
|---|
| 324 | #define FLAG_SNF 0x010 // Result SNAN |
|---|
| 325 | #define FLAG_QNF 0x020 // Result QNAN |
|---|
| 326 | #define FLAG_ZF 0x040 // Result is nul |
|---|
| 327 | #define FLAG_IXF 0x080 // Result is inexact |
|---|
| 328 | #define FLAG_IVF 0x100 // Result is invalid |
|---|
| 329 | #define FLAG_INF 0x200 // Result is infinite |
|---|
| 330 | #define FLAG_DZF 0x400 // Division by zero |
|---|
| 331 | |
|---|
| 332 | // Position of flag in "rename register SR" (NOT IN "SR") |
|---|
| 333 | #define FLAG_POS_F 0x0 // Conditionnal branch flag |
|---|
| 334 | #define FLAG_POS_CY 0x1 // Carry was produced by last arithmétic operation |
|---|
| 335 | #define FLAG_POS_OV 0x0 // Overflow occured during last arithmetic operation |
|---|
| 336 | |
|---|
| 337 | //---------------------------------------------------- |
|---|
| 338 | // Instruction type |
|---|
| 339 | //---------------------------------------------------- |
|---|
| 340 | |
|---|
| 341 | #define M_CPU_LOG2_NB_TYPE 4 |
|---|
| 342 | |
|---|
| 343 | #define TYPE_NOP 0x0 |
|---|
| 344 | #define TYPE_ALU_F 0x1 // Instruction ALU with flag using (ADD, SUB, ADDC ...) |
|---|
| 345 | #define TYPE_ALU_NF 0x2 // Instruction ALU without flag using (AND, OR ...) |
|---|
| 346 | #define TYPE_MAC 0x3 // Instruction ALU with utilisation of register HI/LO |
|---|
| 347 | #define TYPE_J 0x4 // Branch instruction |
|---|
| 348 | #define TYPE_SPR_READ 0x5 // Instruction special : l.mfspr |
|---|
| 349 | #define TYPE_SPR_WRITE 0x6 // Instruction special : l.mtspr |
|---|
| 350 | #define TYPE_SPECIAL 0x7 // Instruction execute in decode stage |
|---|
| 351 | #define TYPE_CUSTOM 0x8 // Instruction Custom |
|---|
| 352 | |
|---|
| 353 | #define TYPE_LOAD_Z 0x9 // Load access (extended by zero) |
|---|
| 354 | #define TYPE_LOAD_S 0xa // Load access (sign extended) |
|---|
| 355 | #define TYPE_STORE 0xc // Store access |
|---|
| 356 | |
|---|
| 357 | //---------------------------------------------------- |
|---|
| 358 | // Condition to branch |
|---|
| 359 | //---------------------------------------------------- |
|---|
| 360 | |
|---|
| 361 | #define M_CPU_LOG2_NB_COND 4 |
|---|
| 362 | |
|---|
| 363 | #define COND_NONE 0x0 // None condition (jump) |
|---|
| 364 | #define COND_F 0x2 // Branch if Flag is set |
|---|
| 365 | #define COND_NF 0x3 // Branch if Flag is clear |
|---|
| 366 | #define COND_REG 0x4 // Branch if a register is read |
|---|
| 367 | #define COND_STACK 0x8 // Branch with pop in stack pointer |
|---|
| 368 | |
|---|
| 369 | //---------------------------------------------------- |
|---|
| 370 | // Event : State and Type |
|---|
| 371 | //---------------------------------------------------- |
|---|
| 372 | |
|---|
| 373 | #define EVENT_STATE_NO_EVENT 0 // no event : current case |
|---|
| 374 | #define EVENT_STATE_EVENT 1 // Have a event : make necessary to manage the event |
|---|
| 375 | #define EVENT_STATE_WAITEND 2 // Wait end of manage event (restaure a good context) |
|---|
| 376 | #define EVENT_STATE_END 3 // CPU can continue |
|---|
| 377 | |
|---|
| 378 | #define EVENT_TYPE_MISS 0 // miss of speculation |
|---|
| 379 | #define EVENT_TYPE_EXCP 1 // exception or interruption occure |
|---|
| 380 | |
|---|
| 381 | // SPEC? TAKE? |
|---|
| 382 | #define BRANCH_STATE_NONE 0 // 0 0 |
|---|
| 383 | #define BRANCH_STATE_NSPEC_TAKE 1 // 0 1 -> incondionnal |
|---|
| 384 | #define BRANCH_STATE_SPEC_NTAKE 2 // 1 0 |
|---|
| 385 | #define BRANCH_STATE_SPEC_TAKE 3 // 1 1 |
|---|
| 386 | |
|---|
| 387 | //---------------------------------------------------- |
|---|
| 388 | // Name to particular register |
|---|
| 389 | //---------------------------------------------------- |
|---|
| 390 | |
|---|
| 391 | //~~~~~~~~~~~~~~~~~~~~~~~~~~ |
|---|
| 392 | // GENERAL PURPOSE REGISTER |
|---|
| 393 | //~~~~~~~~~~~~~~~~~~~~~~~~~~ |
|---|
| 394 | #define M_CPU_LOG2_NB_GPR_LOG 5 |
|---|
| 395 | #define M_CPU_NB_GPR_LOG (1<<M_CPU_LOG2_NB_GPR_LOG) |
|---|
| 396 | |
|---|
| 397 | #define GPR_LOG_LR 0x09 // Link register |
|---|
| 398 | #define REG_PHY_SR 0x00 // Status register |
|---|
| 399 | |
|---|
| 400 | //~~~~~~~~~~~~~~~~~~~~~~~~~~ |
|---|
| 401 | // SPECIAL PURPOSE REGISTER |
|---|
| 402 | //~~~~~~~~~~~~~~~~~~~~~~~~~~ |
|---|
| 403 | #define M_CPU_LOG2_NB_SPR_LOG 1 |
|---|
| 404 | #define M_CPU_NB_SPR_LOG (1<<M_CPU_LOG2_NB_SPR_LOG) |
|---|
| 405 | #define M_CPU_SPR_SIZE_DATA 2 // Size of the most great register |
|---|
| 406 | |
|---|
| 407 | #define SPR_LOG_SR_F 0x00 // Status register bit F (size = 1) |
|---|
| 408 | #define SPR_LOG_SR_CY_OV 0x01 // Status register bit overflow and carry (size = 2) |
|---|
| 409 | //#define SPR_LOG_SR_LO 0x02 // MAC LSB (size = 32) |
|---|
| 410 | //#define SPR_LOG_SR_HI 0x03 // MAC MSB (size = 32) |
|---|
| 411 | */ |
|---|
| 412 | |
|---|
| 413 | /* |
|---|
| 414 | //---------------------------------------------------- |
|---|
| 415 | // Code Operation (before decode) |
|---|
| 416 | //---------------------------------------------------- |
|---|
| 417 | |
|---|
| 418 | // Codop - [31:26] Instructions with immediat |
|---|
| 419 | #define OPCOD_L_J 0x00 // 000_000 |
|---|
| 420 | #define OPCOD_L_JAL 0x01 // 000_001 |
|---|
| 421 | #define OPCOD_L_BNF 0x03 // 000_011 |
|---|
| 422 | #define OPCOD_L_BF 0x04 // 000_100 |
|---|
| 423 | #define OPCOD_L_RFE 0x09 // 001_001 |
|---|
| 424 | #define OPCOD_L_JR 0x11 // 010_001 |
|---|
| 425 | #define OPCOD_L_JALR 0x12 // 010_010 |
|---|
| 426 | #define OPCOD_L_MACI 0x13 // 010_011 |
|---|
| 427 | #define OPCOD_L_CUST1 0x1c // 011_100 |
|---|
| 428 | #define OPCOD_L_CUST2 0x1d // 011_101 |
|---|
| 429 | #define OPCOD_L_CUST3 0x1e // 011_110 |
|---|
| 430 | #define OPCOD_L_CUST4 0x1f // 011_111 |
|---|
| 431 | #define OPCOD_L_CUST5 0x3c // 111_100 |
|---|
| 432 | #define OPCOD_L_CUST6 0x3d // 111_101 |
|---|
| 433 | #define OPCOD_L_CUST7 0x3e // 111_110 |
|---|
| 434 | #define OPCOD_L_CUST8 0x3f // 111_111 |
|---|
| 435 | #define OPCOD_L_LD 0x20 // 100_000 |
|---|
| 436 | #define OPCOD_L_LWZ 0x21 // 100_001 |
|---|
| 437 | #define OPCOD_L_LWS 0x22 // 100_010 |
|---|
| 438 | #define OPCOD_L_LBZ 0x23 // 100_011 |
|---|
| 439 | #define OPCOD_L_LBS 0x24 // 100_100 |
|---|
| 440 | #define OPCOD_L_LHZ 0x25 // 100_101 |
|---|
| 441 | #define OPCOD_L_LHS 0x26 // 100_110 |
|---|
| 442 | #define OPCOD_L_ADDI 0x27 // 100_111 |
|---|
| 443 | #define OPCOD_L_ADDIC 0x28 // 101_000 |
|---|
| 444 | #define OPCOD_L_ANDI 0x29 // 101_001 |
|---|
| 445 | #define OPCOD_L_ORI 0x2a // 101_010 |
|---|
| 446 | #define OPCOD_L_XORI 0x2b // 101_011 |
|---|
| 447 | #define OPCOD_L_MULI 0x2c // 101_100 |
|---|
| 448 | #define OPCOD_L_MFSPR 0x2d // 101_101 |
|---|
| 449 | #define OPCOD_L_MTSPR 0x30 // 110_000 |
|---|
| 450 | #define OPCOD_L_SD 0x32 // 110_010 |
|---|
| 451 | #define OPCOD_L_SW 0x35 // 110_101 |
|---|
| 452 | #define OPCOD_L_SB 0x36 // 110_110 |
|---|
| 453 | #define OPCOD_L_SH 0x37 // 110_111 |
|---|
| 454 | |
|---|
| 455 | #define OPCOD_INST_LV 0x0a // 001_010 // Instruction ORVDX64 |
|---|
| 456 | #define OPCOD_INST_LF 0x33 // 110_011 // Instruction ORFPX32/64 |
|---|
| 457 | |
|---|
| 458 | #define OPCOD_SPECIAL 0x38 // 111_000 // Instructions Register-Register |
|---|
| 459 | #define OPCOD_SPECIAL_1 0x39 // 111_001 // Instructions "set flag" with register |
|---|
| 460 | #define OPCOD_SPECIAL_2 0x2f // 101_111 // Instructions "set flag" with immediat |
|---|
| 461 | #define OPCOD_SPECIAL_6 0x2e // 101_110 // Instruction Shift/Rotate with immediat |
|---|
| 462 | #define OPCOD_SPECIAL_7 0x31 // 110_001 // Instructions multiply with HI-LO |
|---|
| 463 | #define OPCOD_SPECIAL_8 0x06 // 000_110 // Instructions acces at HI-LO |
|---|
| 464 | |
|---|
| 465 | // OPCOD_SPECIAL instructions - [9:8] [3:0] Instructions Register-Register |
|---|
| 466 | #define OPCOD_L_ADD 0x00 // 00_0000 |
|---|
| 467 | #define OPCOD_L_ADDC 0x01 // 00_0001 |
|---|
| 468 | #define OPCOD_L_SUB 0x02 // 00_0010 |
|---|
| 469 | #define OPCOD_L_AND 0x03 // 00_0011 |
|---|
| 470 | #define OPCOD_L_OR 0x04 // 00_0100 |
|---|
| 471 | #define OPCOD_L_XOR 0x05 // 00_0101 |
|---|
| 472 | #define OPCOD_L_CMOV 0x0e // 00_1110 |
|---|
| 473 | #define OPCOD_L_FF1 0x0f // 00_1111 |
|---|
| 474 | #define OPCOD_L_FL1 0x1f // 01_1111 |
|---|
| 475 | #define OPCOD_L_MUL 0x36 // 11_0110 |
|---|
| 476 | #define OPCOD_L_DIV 0x39 // 11_1001 |
|---|
| 477 | #define OPCOD_L_DIVU 0x3a // 11_1010 |
|---|
| 478 | #define OPCOD_L_MULU 0x3b // 11_1011 |
|---|
| 479 | |
|---|
| 480 | #define OPCOD_SPECIAL_3 0xc // 1100 // Instructions extend |
|---|
| 481 | #define OPCOD_SPECIAL_4 0xd // 1101 // Instructions extend (64b) |
|---|
| 482 | #define OPCOD_SPECIAL_5 0x8 // 1000 // Instruction Shift/Rotate with register |
|---|
| 483 | |
|---|
| 484 | // OPCOD_SPECIAL_1 instructions - [25:21] Instructions "set flag" with register |
|---|
| 485 | #define OPCOD_L_SFEQ 0x00 // 00000 |
|---|
| 486 | #define OPCOD_L_SFNE 0x01 // 00001 |
|---|
| 487 | #define OPCOD_L_SFGTU 0x02 // 00010 |
|---|
| 488 | #define OPCOD_L_SFGEU 0x03 // 00011 |
|---|
| 489 | #define OPCOD_L_SFLTU 0x04 // 00100 |
|---|
| 490 | #define OPCOD_L_SFLEU 0x05 // 00101 |
|---|
| 491 | #define OPCOD_L_SFGTS 0x0a // 01010 |
|---|
| 492 | #define OPCOD_L_SFGES 0x0b // 01011 |
|---|
| 493 | #define OPCOD_L_SFLTS 0x0c // 01100 |
|---|
| 494 | #define OPCOD_L_SFLES 0x0d // 01101 |
|---|
| 495 | |
|---|
| 496 | // OPCOD_SPECIAL_2 instructions - [25:21] Instructions "set flag" with immediat |
|---|
| 497 | #define OPCOD_L_SFEQI 0x00 // 00000 |
|---|
| 498 | #define OPCOD_L_SFNEI 0x01 // 00001 |
|---|
| 499 | #define OPCOD_L_SFGTUI 0x02 // 00010 |
|---|
| 500 | #define OPCOD_L_SFGEUI 0x03 // 00011 |
|---|
| 501 | #define OPCOD_L_SFLTUI 0x04 // 00100 |
|---|
| 502 | #define OPCOD_L_SFLEUI 0x05 // 00101 |
|---|
| 503 | #define OPCOD_L_SFGTSI 0x0a // 01010 |
|---|
| 504 | #define OPCOD_L_SFGESI 0x0b // 01011 |
|---|
| 505 | #define OPCOD_L_SFLTSI 0x0c // 01100 |
|---|
| 506 | #define OPCOD_L_SFLESI 0x0d // 01101 |
|---|
| 507 | |
|---|
| 508 | // OPCOD_SPECIAL_3 instructions - [9:6] Instructions extend |
|---|
| 509 | #define OPCOD_L_EXTHS 0x0 // 0000 |
|---|
| 510 | #define OPCOD_L_EXTHZ 0x2 // 0010 |
|---|
| 511 | #define OPCOD_L_EXTBS 0x1 // 0001 |
|---|
| 512 | #define OPCOD_L_EXTBZ 0x3 // 0011 |
|---|
| 513 | |
|---|
| 514 | // OPCOD_SPECIAL_4 instructions - [9:6] Instructions extend (64b) |
|---|
| 515 | #define OPCOD_L_EXTWS 0x0 // 0000 |
|---|
| 516 | #define OPCOD_L_EXTWZ 0x1 // 0001 |
|---|
| 517 | |
|---|
| 518 | // OPCOD_SPECIAL_5 instructions - [7:6] Instruction Shift/Rotate with register |
|---|
| 519 | #define OPCOD_L_SLL 0x0 // 00 |
|---|
| 520 | #define OPCOD_L_SRL 0x1 // 01 |
|---|
| 521 | #define OPCOD_L_SRA 0x2 // 10 |
|---|
| 522 | #define OPCOD_L_ROR 0x3 // 11 |
|---|
| 523 | |
|---|
| 524 | // OPCOD_SPECIAL_6 instructions - [7:6] Instruction Shift/Rotate with immediat |
|---|
| 525 | #define OPCOD_L_SLLI 0x0 // 00 |
|---|
| 526 | #define OPCOD_L_SRLI 0x1 // 01 |
|---|
| 527 | #define OPCOD_L_SRAI 0x2 // 10 |
|---|
| 528 | #define OPCOD_L_RORI 0x3 // 11 |
|---|
| 529 | |
|---|
| 530 | // OPCOD_SPECIAL_7 instructions - [3:0] Instructions multiply with HI-LO |
|---|
| 531 | #define OPCOD_L_MAC 0x1 // 0001 |
|---|
| 532 | #define OPCOD_L_MSB 0x2 // 0010 |
|---|
| 533 | |
|---|
| 534 | // OPCOD_SPECIAL_8 instructions - [17] Instructions acces at HI-LO |
|---|
| 535 | #define OPCOD_L_MOVHI 0x0 // 0 |
|---|
| 536 | #define OPCOD_L_MACRC 0x1 // 1 |
|---|
| 537 | |
|---|
| 538 | // Particular case Instructions systems |
|---|
| 539 | #define OPCOD_L_MSYNC 0x22000000 |
|---|
| 540 | #define OPCOD_L_CSYNC 0x23000000 |
|---|
| 541 | #define OPCOD_L_PSYNC 0x22800000 |
|---|
| 542 | #define OPCOD_L_NOP 0x1500 |
|---|
| 543 | #define OPCOD_L_SYS 0x2000 |
|---|
| 544 | #define OPCOD_L_TRAP 0x2100 |
|---|
| 545 | |
|---|
| 546 | //---------------------------------------------------- |
|---|
| 547 | // Code Operation (after decode) |
|---|
| 548 | //---------------------------------------------------- |
|---|
| 549 | |
|---|
| 550 | typedef enum |
|---|
| 551 | { |
|---|
| 552 | // ##### WARNING : This opcode must be the first##### |
|---|
| 553 | INST_L_NO_IMPLEMENTED , // Operation is not implemented |
|---|
| 554 | |
|---|
| 555 | INST_L_ADD , // L.ADD , L.ADDI , L.ADDC , L.ADDIC |
|---|
| 556 | INST_L_AND , // L.AND , L.ANDI |
|---|
| 557 | INST_L_OR , // L.OR , L.ORI |
|---|
| 558 | INST_L_XOR , // L.XOR , L.XORI |
|---|
| 559 | INST_L_CMOV , // L.CMOV |
|---|
| 560 | INST_L_SUB , // L.SUB |
|---|
| 561 | INST_L_FF1 , // L.FF1 |
|---|
| 562 | INST_L_EXTBS , // L.EXTBS |
|---|
| 563 | INST_L_EXTBZ , // L.EXTBZ |
|---|
| 564 | INST_L_EXTHS , // L.EXTHS |
|---|
| 565 | INST_L_EXTHZ , // L.EXTHZ |
|---|
| 566 | INST_L_EXTWS , // L.EXTWS |
|---|
| 567 | INST_L_EXTWZ , // L.EXTWZ |
|---|
| 568 | INST_L_e , // |
|---|
| 569 | INST_L_f , // |
|---|
| 570 | INST_L_MUL , // L.MUL , L.MULI |
|---|
| 571 | INST_L_MULU , // L.MULU |
|---|
| 572 | INST_L_DIV , // L.DIV |
|---|
| 573 | INST_L_DIVU , // L.DIVU |
|---|
| 574 | INST_L_SLL , // L.SLL , L.SLLI |
|---|
| 575 | INST_L_SRL , // L.SRL , L.SRLI |
|---|
| 576 | INST_L_SRA , // L.SRA , L.SRAI |
|---|
| 577 | INST_L_ROR , // L.ROR , L.RORI |
|---|
| 578 | INST_L_SFGES , // L.SFGES , L.SFGESI |
|---|
| 579 | INST_L_SFGEU , // L.SFGEU , L.SFGEUI |
|---|
| 580 | INST_L_SFGTS , // L.SFGTS , L.SFGTSI |
|---|
| 581 | INST_L_SFGTU , // L.SFGTU , L.SFGTUI |
|---|
| 582 | INST_L_SFLES , // L.SFLES , L.SFLESI |
|---|
| 583 | INST_L_SFLEU , // L.SFLEU , L.SFLEUI |
|---|
| 584 | INST_L_SFLTS , // L.SFLTS , L.SFLTSI |
|---|
| 585 | INST_L_SFLTU , // L.SFLTU , L.SFLTUI |
|---|
| 586 | INST_L_SFEQ , // L.SFEQ , L.SFEQI |
|---|
| 587 | INST_L_SFNE , // L.SFNE , L.SFNEI |
|---|
| 588 | INST_L_READ , // L.BNF , L.BF , L.JR |
|---|
| 589 | INST_L_MOVHI , // L.MOVI |
|---|
| 590 | INST_L_CSYNC , // L.CSYNC |
|---|
| 591 | INST_L_MSYNC , // L.MSYNC |
|---|
| 592 | INST_L_PSYNC , // L.PSYNC |
|---|
| 593 | INST_L_RFE , // L.RFE |
|---|
| 594 | INST_L_MAC , // L.MAC , L.MACI |
|---|
| 595 | INST_L_MSB , // L.MSB |
|---|
| 596 | INST_L_MACRC , // L.MACRC |
|---|
| 597 | INST_L_2b , // |
|---|
| 598 | INST_L_MEMB , // L.LBS , L.LBZ , L.SB |
|---|
| 599 | INST_L_MEMH , // L.LHS , L.LHZ , L.SH |
|---|
| 600 | INST_L_MEMW , // L.LWS , L.LWZ , L.SW |
|---|
| 601 | INST_L_MEMD , // L.LD , L.SD |
|---|
| 602 | INST_L_CUST1 , // L.CUST1 |
|---|
| 603 | INST_L_CUST2 , // L.CUST2 |
|---|
| 604 | INST_L_CUST3 , // L.CUST3 |
|---|
| 605 | INST_L_CUST4 , // L.CUST4 |
|---|
| 606 | INST_L_CUST5 , // L.CUST5 |
|---|
| 607 | INST_L_CUST6 , // L.CUST6 |
|---|
| 608 | INST_L_CUST7 , // L.CUST7 |
|---|
| 609 | INST_L_CUST8 , // L.CUST8 |
|---|
| 610 | INST_L_38 , // |
|---|
| 611 | INST_L_39 , // |
|---|
| 612 | INST_L_3a , // |
|---|
| 613 | INST_L_3b , // |
|---|
| 614 | INST_L_3c , // |
|---|
| 615 | INST_L_3d , // |
|---|
| 616 | INST_L_3e , // |
|---|
| 617 | INST_NOP // L.NOP |
|---|
| 618 | } opcod_t; |
|---|
| 619 | |
|---|
| 620 | #define LOG2_NB_INST_L 6 |
|---|
| 621 | #define NB_INST_L 64 // +1 -> INST_L_NO_IMPLEMENTED |
|---|
| 622 | //#define NB_INST_L (INST_L_NO_IMPLEMENTED+1) |
|---|
| 623 | */ |
|---|
| 624 | |
|---|
| 625 | }; // end namespace behavioural |
|---|
| 626 | }; // end namespace morpheo |
|---|
| 627 | |
|---|
| 628 | #endif |
|---|
