1 | #ifndef morpheo_behavioural_Constants_h |
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2 | #define morpheo_behavioural_Constants_h |
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3 | |
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4 | /* |
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5 | WARNING : |
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6 | |
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7 | I Use reserved exception : |
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8 | |
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9 | 0x10 - EXCEPTION_MEMORY_MISS_SPECULATION - Load miss speculation |
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10 | 0x11 - EXCEPTION_MEMORY_LOAD_SPECULATIVE - The load is speculative : write in register file, but don't commit |
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11 | 0x12 - EXCEPTION_ALU_SPR_ACCESS_INVALID - SPR present in ALU but not compatible privilege |
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12 | 0x13 - EXCEPTION_ALU_SPR_ACCESS_MUST_READ - SPR not present in ALU |
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13 | 0x14 - EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE - SPR not present in ALU |
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14 | |
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15 | I Use reserved SPR : |
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16 | [0][21] - SPR_CID : Context Id |
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17 | [0][22] - SPR_TID : Thread Id |
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18 | [0][23] - SPR_TSR : Thread Status Register (Priority) |
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19 | */ |
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20 | |
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21 | #include "Common/include/ToString.h" |
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22 | |
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23 | namespace morpheo { |
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24 | namespace behavioural { |
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25 | |
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26 | # define SET_FLAG( x,pos) {(x) |= (1<<(pos));} while (0) |
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27 | # define UNSET_FLAG( x,pos) {(x) &= ~(1<<(pos));} while (0) |
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28 | # define IS_SET_FLAG( x,pos) (((x) & (1<<(pos))) != 0) |
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29 | # define IS_UNSET_FLAG(x,pos) (((x) & (1<<(pos))) == 0) |
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30 | # define CHANGE_FLAG( x,pos,f) \ |
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31 | { \ |
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32 | if (f) \ |
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33 | {SET_FLAG(x,pos);} \ |
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34 | else \ |
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35 | {UNSET_FLAG(x,pos);} \ |
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36 | } while (0) |
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37 | |
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38 | //=========================================================[ Type ]===== |
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39 | typedef enum |
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40 | { |
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41 | TYPE_ALU = 0x0, // 0000 - unit multiple |
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42 | TYPE_SHIFT = 0x1, // 0000 - unit multiple |
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43 | TYPE_MOVE = 0x2, // 0000 - unit multiple |
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44 | TYPE_TEST = 0x3, // 0000 - unit multiple |
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45 | TYPE_MUL = 0x4, // 0000 - unit multiple |
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46 | TYPE_DIV = 0x5, // 0000 - unit multiple, type optionnal |
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47 | TYPE_EXTEND = 0x6, // 0000 - unit multiple, type optionnal |
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48 | TYPE_FIND = 0x7, // 0000 - unit multiple, type optionnal |
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49 | TYPE_SPECIAL = 0x8, // 0000 - unit uniq |
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50 | TYPE_CUSTOM = 0x9, // 0000 - unit uniq , type optionnal |
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51 | TYPE_BRANCH = 0xa, // 0000 - unit multiple |
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52 | TYPE_MEMORY = 0xb, // 0000 - unit uniq , type exclusive |
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53 | TYPE_INVALID = 0xf // 1111 - none |
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54 | } type_t; |
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55 | |
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56 | //#define NB_TYPE 11 |
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57 | # define SIZE_TYPE 5 |
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58 | # define MAX_TYPE (1<<SIZE_TYPE) |
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59 | |
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60 | // TYPE | multiple? | Optionnal? | Exclusive? | Comment |
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61 | //--------------+-----------+------------+------------+--------- |
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62 | // TYPE_ALU | X | | | |
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63 | // TYPE_SHIFT | X | | | ror is optionnal |
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64 | // TYPE_MOVE | X | | | cmov is optionnal |
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65 | // TYPE_TEST | X | | | |
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66 | // TYPE_MUL | X | | | |
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67 | // TYPE_DIV | X | X | | |
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68 | // TYPE_EXTEND | X | X | | |
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69 | // TYPE_FIND | X | X | | |
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70 | // TYPE_SPECIAL | | | | mac unit is optionnal |
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71 | // TYPE_CUSTOM | | X | | |
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72 | // TYPE_BRANCH | X | | | |
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73 | // TYPE_MEMORY | | | X | |
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74 | |
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75 | # define is_type_valid(x) \ |
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76 | ((x == TYPE_ALU ) or \ |
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77 | (x == TYPE_SHIFT ) or \ |
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78 | (x == TYPE_MOVE ) or \ |
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79 | (x == TYPE_TEST ) or \ |
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80 | (x == TYPE_MUL ) or \ |
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81 | (x == TYPE_DIV ) or \ |
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82 | (x == TYPE_EXTEND ) or \ |
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83 | (x == TYPE_FIND ) or \ |
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84 | (x == TYPE_SPECIAL) or \ |
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85 | (x == TYPE_CUSTOM ) or \ |
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86 | (x == TYPE_BRANCH ) or \ |
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87 | (x == TYPE_MEMORY )) |
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88 | |
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89 | # define is_type_uniq(x) \ |
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90 | ((x == TYPE_SPECIAL) or \ |
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91 | (x == TYPE_CUSTOM ) or \ |
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92 | (x == TYPE_MEMORY )) |
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93 | |
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94 | # define is_type_optionnal(x) \ |
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95 | ((x == TYPE_DIV ) or \ |
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96 | (x == TYPE_EXTEND ) or \ |
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97 | (x == TYPE_FIND ) or \ |
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98 | (x == TYPE_CUSTOM )) |
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99 | |
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100 | # define is_type_exclusive(x) \ |
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101 | ((x == TYPE_MEMORY )) |
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102 | |
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103 | //====================================================[ Operation ]===== |
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104 | |
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105 | //-------------------------------------------------------[ Memory ]----- |
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106 | # define OPERATION_MEMORY_LOAD_8_Z 0x08 // 0_1000 |
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107 | # define OPERATION_MEMORY_LOAD_16_Z 0x09 // 0_1001 |
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108 | # define OPERATION_MEMORY_LOAD_32_Z 0x0a // 0_1010 |
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109 | # define OPERATION_MEMORY_LOAD_64_Z 0x0b // 0_1011 |
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110 | # define OPERATION_MEMORY_LOAD_8_S 0x18 // 1_1000 |
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111 | # define OPERATION_MEMORY_LOAD_16_S 0x19 // 1_1001 |
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112 | # define OPERATION_MEMORY_LOAD_32_S 0x1a // 1_1010 |
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113 | # define OPERATION_MEMORY_LOAD_64_S 0x1b // 1_1011 |
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114 | |
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115 | # define OPERATION_MEMORY_STORE_8 0x0c // 0_1100 |
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116 | # define OPERATION_MEMORY_STORE_16 0x0d // 0_1101 |
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117 | # define OPERATION_MEMORY_STORE_32 0x0e // 0_1110 |
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118 | # define OPERATION_MEMORY_STORE_64 0x0f // 0_1111 |
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119 | # define OPERATION_MEMORY_STORE_HEAD_OK 0x1c // 1_1100 |
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120 | # define OPERATION_MEMORY_STORE_HEAD_KO 0x1d // 1_1101 |
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121 | |
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122 | # define OPERATION_MEMORY_LOCK 0x01 // 0_0001 |
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123 | # define OPERATION_MEMORY_INVALIDATE 0x02 // 0_0010 |
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124 | # define OPERATION_MEMORY_PREFETCH 0x03 // 0_0011 |
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125 | # define OPERATION_MEMORY_FLUSH 0x06 // 0_0110 |
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126 | # define OPERATION_MEMORY_SYNCHRONIZATION 0x07 // 0_0111 |
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127 | |
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128 | #define is_operation_memory_load(x) \ |
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129 | ((x == OPERATION_MEMORY_LOAD_8_Z ) or \ |
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130 | (x == OPERATION_MEMORY_LOAD_16_Z) or \ |
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131 | (x == OPERATION_MEMORY_LOAD_32_Z) or \ |
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132 | (x == OPERATION_MEMORY_LOAD_64_Z) or \ |
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133 | (x == OPERATION_MEMORY_LOAD_8_S ) or \ |
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134 | (x == OPERATION_MEMORY_LOAD_16_S) or \ |
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135 | (x == OPERATION_MEMORY_LOAD_32_S) or \ |
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136 | (x == OPERATION_MEMORY_LOAD_64_S) ) |
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137 | |
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138 | #define is_operation_memory_store(x) \ |
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139 | ((x == OPERATION_MEMORY_STORE_8 ) or \ |
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140 | (x == OPERATION_MEMORY_STORE_16 ) or \ |
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141 | (x == OPERATION_MEMORY_STORE_32 ) or \ |
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142 | (x == OPERATION_MEMORY_STORE_64 ) or \ |
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143 | (x == OPERATION_MEMORY_STORE_HEAD_OK) or \ |
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144 | (x == OPERATION_MEMORY_STORE_HEAD_KO)) |
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145 | |
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146 | #define is_operation_memory_store_head(x) \ |
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147 | ((x == OPERATION_MEMORY_STORE_HEAD_OK) or \ |
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148 | (x == OPERATION_MEMORY_STORE_HEAD_KO)) |
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149 | |
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150 | #define is_operation_memory_load_signed(x) \ |
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151 | ((x == OPERATION_MEMORY_LOAD_8_S ) or \ |
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152 | (x == OPERATION_MEMORY_LOAD_16_S) or \ |
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153 | (x == OPERATION_MEMORY_LOAD_32_S) or \ |
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154 | (x == OPERATION_MEMORY_LOAD_64_S) ) |
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155 | |
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156 | # define MEMORY_ACCESS_8 0x0 |
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157 | # define MEMORY_ACCESS_16 0x1 |
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158 | # define MEMORY_ACCESS_32 0x2 |
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159 | # define MEMORY_ACCESS_64 0x3 |
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160 | |
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161 | # define MEMORY_SIZE_8 8 |
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162 | # define MEMORY_SIZE_16 16 |
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163 | # define MEMORY_SIZE_32 32 |
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164 | # define MEMORY_SIZE_64 64 |
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165 | |
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166 | # define MASK_MEMORY_ACCESS_8 0x0 |
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167 | # define MASK_MEMORY_ACCESS_16 0x1 |
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168 | # define MASK_MEMORY_ACCESS_32 0x3 |
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169 | # define MASK_MEMORY_ACCESS_64 0x7 |
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170 | |
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171 | #define memory_size(x) \ |
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172 | (((x==OPERATION_MEMORY_LOAD_16_Z)or \ |
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173 | (x==OPERATION_MEMORY_LOAD_16_S)or \ |
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174 | (x==OPERATION_MEMORY_STORE_16 ))?MEMORY_SIZE_16: \ |
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175 | (((x==OPERATION_MEMORY_LOAD_32_Z)or \ |
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176 | (x==OPERATION_MEMORY_LOAD_32_S)or \ |
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177 | (x==OPERATION_MEMORY_STORE_32 ))?MEMORY_SIZE_32: \ |
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178 | (((x==OPERATION_MEMORY_LOAD_64_Z)or \ |
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179 | (x==OPERATION_MEMORY_LOAD_64_S)or \ |
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180 | (x==OPERATION_MEMORY_STORE_64 ))?MEMORY_SIZE_64:MEMORY_SIZE_8))) |
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181 | |
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182 | #define memory_access(x) \ |
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183 | (((x==OPERATION_MEMORY_LOAD_16_Z)or \ |
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184 | (x==OPERATION_MEMORY_LOAD_16_S)or \ |
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185 | (x==OPERATION_MEMORY_STORE_16 ))?MEMORY_ACCESS_16: \ |
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186 | (((x==OPERATION_MEMORY_LOAD_32_Z)or \ |
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187 | (x==OPERATION_MEMORY_LOAD_32_S)or \ |
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188 | (x==OPERATION_MEMORY_STORE_32 ))?MEMORY_ACCESS_32: \ |
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189 | (((x==OPERATION_MEMORY_LOAD_64_Z)or \ |
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190 | (x==OPERATION_MEMORY_LOAD_64_S)or \ |
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191 | (x==OPERATION_MEMORY_STORE_64 ))?MEMORY_ACCESS_64:MEMORY_ACCESS_8))) |
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192 | |
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193 | #define mask_memory_access(x) \ |
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194 | (((x==OPERATION_MEMORY_LOAD_16_Z)or \ |
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195 | (x==OPERATION_MEMORY_LOAD_16_S)or \ |
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196 | (x==OPERATION_MEMORY_STORE_16 ))?MASK_MEMORY_ACCESS_16: \ |
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197 | (((x==OPERATION_MEMORY_LOAD_32_Z)or \ |
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198 | (x==OPERATION_MEMORY_LOAD_32_S)or \ |
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199 | (x==OPERATION_MEMORY_STORE_32 ))?MASK_MEMORY_ACCESS_32: \ |
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200 | (((x==OPERATION_MEMORY_LOAD_64_Z)or \ |
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201 | (x==OPERATION_MEMORY_LOAD_64_S)or \ |
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202 | (x==OPERATION_MEMORY_STORE_64 ))?MASK_MEMORY_ACCESS_64:MASK_MEMORY_ACCESS_8))) |
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203 | |
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204 | //---------------------------------------------[ Functionnal Unit ]----- |
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205 | |
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206 | // WARNING : Operations are coded in a one-hot implementation that is used in the functional unit's vhdl code. |
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207 | // Do not change that (you can still change the values as long as it respects the one-hot encoding). |
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208 | |
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209 | # define OPERATION_ALU_L_ADD 0x1 // 000_0001 l.add , l.addi |
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210 | # define OPERATION_ALU_L_ADDC 0x2 // 000_0010 l.addc , l.addic |
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211 | # define OPERATION_ALU_L_SUB 0x4 // 000_0100 l.sub |
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212 | # define OPERATION_ALU_L_AND 0x8 // 000_1000 l.and , l.andi |
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213 | # define OPERATION_ALU_L_OR 0x10 // 001_0000 l.or , l.ori |
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214 | # define OPERATION_ALU_L_XOR 0x20 // 010_0000 l.xor , l.xori |
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215 | |
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216 | // WARNING : Shift and rotate operation codes are hard-coded in the functional unit's vhdl code, |
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217 | // with bit 0 corresponding to the direction (0 for right, and 1 for left), |
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218 | // bit 1 to the type (0 for shift, 1 for rotate) and bit 2 is to be set to 0 for a logic |
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219 | // operation and 1 for an arithmetic operation. |
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220 | // Do not change that (unless you respect the one-hot encoding described above). |
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221 | |
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222 | # define OPERATION_SHIFT_L_SLL 0x1 // 000_0001 l.sll , l.slli |
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223 | # define OPERATION_SHIFT_L_SRA 0x4 // 000_0100 l.sra , l.srai |
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224 | # define OPERATION_SHIFT_L_SRL 0x0 // 000_0000 l.srl , l.srli |
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225 | # define OPERATION_SHIFT_L_ROR 0x2 // 000_0010 l.ror , l.rori |
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226 | |
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227 | # define OPERATION_MOVE_L_MOVHI 0x1 // 000_0001 l.movhi |
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228 | # define OPERATION_MOVE_L_CMOV 0x2 // 000_0010 l.cmov |
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229 | |
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230 | # define OPERATION_TEST_L_SFGES 0x45 // 100_0101 l.sfges , l.sfges |
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231 | # define OPERATION_TEST_L_SFGEU 0x5 // 000_0101 l.sfgeu , l.sfgeu |
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232 | # define OPERATION_TEST_L_SFGTS 0x46 // 100_0110 L.sfgts , l.sfgts |
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233 | # define OPERATION_TEST_L_SFGTU 0x6 // 000_0110 l.sfgtu , l.sfgtu |
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234 | # define OPERATION_TEST_L_SFLES 0x49 // 100_1001 l.sfles , l.sfles |
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235 | # define OPERATION_TEST_L_SFLEU 0x9 // 000_1001 l.sfleu , l.sfleu |
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236 | # define OPERATION_TEST_L_SFLTS 0x4A // 100_1010 l.sflts , l.sflts |
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237 | # define OPERATION_TEST_L_SFLTU 0xA // 000_1010 l.sfltu , l.sfltu |
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238 | # define OPERATION_TEST_L_SFEQ 0x10 // 001_0000 l.sfeq , l.sfeqi |
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239 | # define OPERATION_TEST_L_SFNE 0x20 // 010_0000 l.sfne , l.sfnei |
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240 | |
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241 | # define OPERATION_MUL_L_MUL 0x1 // 000_0001 l.mul , l.muli |
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242 | # define OPERATION_MUL_L_MULU 0x2 // 000_0010 l.mulu |
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243 | |
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244 | # define OPERATION_DIV_L_DIV 0x1 // 000_0001 l.div |
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245 | # define OPERATION_DIV_L_DIVU 0x2 // 000_0010 l.divu |
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246 | |
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247 | # define OPERATION_EXTEND_L_EXTEND_Z 0x1 // 000_0001 l.extbz , l.exthz, l.extwz |
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248 | # define OPERATION_EXTEND_L_EXTEND_S 0x2 // 000_0010 l.extbs , l.exths, l.extws |
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249 | |
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250 | # define OPERATION_FIND_L_FF1 0x1 // 000_0001 l.ff1 |
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251 | # define OPERATION_FIND_L_FL1 0x2 // 000_0010 l.fl1 |
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252 | |
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253 | # define OPERATION_SPECIAL_L_NOP 0x7f // 111_1111 l.nop |
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254 | # define OPERATION_SPECIAL_L_MFSPR 0x1 // 000_0001 l.mfspr |
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255 | # define OPERATION_SPECIAL_L_MTSPR 0x2 // 000_0010 l.mtspr |
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256 | # define OPERATION_SPECIAL_L_RFE 0x4 // 000_0100 l.rfe |
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257 | # define OPERATION_SPECIAL_L_MAC 0x11 // 001_0001 l.mac , l.maci |
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258 | # define OPERATION_SPECIAL_L_MACRC 0x12 // 001_0010 l.macrc |
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259 | # define OPERATION_SPECIAL_L_MSB 0x14 // 001_0100 l.msb |
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260 | //#define OPERATION_SPECIAL_L_MSYNC 0x21 // 010_0001 l.msync |
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261 | //#define OPERATION_SPECIAL_L_PSYNC 0x22 // 010_0010 l.psync |
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262 | //#define OPERATION_SPECIAL_L_CSYNC 0x24 // 010_0100 l.csync |
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263 | # define OPERATION_SPECIAL_L_SYS 0x41 // 100_0001 l.sys |
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264 | # define OPERATION_SPECIAL_L_TRAP 0x42 // 100_0010 l.trap |
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265 | |
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266 | # define OPERATION_BRANCH_NONE 0x1 // 000_0001 l.j |
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267 | # define OPERATION_BRANCH_L_TEST_NF 0x2 // 000_0010 l.bnf |
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268 | # define OPERATION_BRANCH_L_TEST_F 0x4 // 000_0100 l.bf |
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269 | # define OPERATION_BRANCH_L_JALR 0x8 // 000_1000 l.jal , l.jalr , l.jr |
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270 | |
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271 | //-------------------------------------------------------[ Custom ]----- |
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272 | |
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273 | # define OPERATION_CUSTOM_L_1 0x40 // 100_0000 |
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274 | # define OPERATION_CUSTOM_L_2 0x41 // 100_0001 |
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275 | # define OPERATION_CUSTOM_L_3 0x42 // 100_0010 |
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276 | # define OPERATION_CUSTOM_L_4 0x43 // 100_0011 |
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277 | # define OPERATION_CUSTOM_L_5 0x44 // 100_0100 |
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278 | # define OPERATION_CUSTOM_L_6 0x45 // 100_0101 |
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279 | # define OPERATION_CUSTOM_L_7 0x46 // 100_0110 |
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280 | # define OPERATION_CUSTOM_L_8 0x47 // 100_0111 |
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281 | # define OPERATION_CUSTOM_LF_1_D 0x48 // 100_1000 |
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282 | # define OPERATION_CUSTOM_LF_1_S 0x49 // 100_1001 |
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283 | # define OPERATION_CUSTOM_LV_1 0x4c // 100_1100 |
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284 | # define OPERATION_CUSTOM_LV_2 0x4d // 100_1101 |
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285 | # define OPERATION_CUSTOM_LV_3 0x4e // 100_1110 |
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286 | # define OPERATION_CUSTOM_LV_4 0x4f // 100_1111 |
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287 | |
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288 | # define SIZE_OPERATION 7 |
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289 | # define MAX_OPERATION (1<<SIZE_OPERATION) |
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290 | |
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291 | //====================================================[ Exception ]===== |
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292 | // Exception - OpenRISC |
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293 | |
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294 | # define SIZE_EXCEPTION 5 |
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295 | # define SIZE_EXCEPTION_USE 4 |
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296 | # define SIZE_EXCEPTION_MEMORY 5 |
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297 | # define SIZE_EXCEPTION_CUSTOM 5 |
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298 | # define SIZE_EXCEPTION_ALU 5 |
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299 | # define SIZE_EXCEPTION_DECOD 5 |
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300 | # define SIZE_EXCEPTION_IFETCH 5 |
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301 | |
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302 | # define EXCEPTION_NONE 0x00 // none exception |
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303 | # define EXCEPTION_RESET 0x01 // software or hardware reset |
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304 | # define EXCEPTION_BUS_ERROR 0x02 // Access at a invalid physical adress |
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305 | # define EXCEPTION_DATA_PAGE 0x03 // No matching or page violation protection in pages tables |
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306 | # define EXCEPTION_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables |
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307 | # define EXCEPTION_TICK_TIMER 0x05 // Tick timer interruption |
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308 | # define EXCEPTION_ALIGNMENT 0x06 // Load/Store access is not aligned |
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309 | # define EXCEPTION_ILLEGAL_INSTRUCTION 0x07 // Instruction is illegal (no implemented) |
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310 | # define EXCEPTION_INTERRUPT 0x08 // External interruption |
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311 | # define EXCEPTION_DATA_TLB 0x09 // DTLB miss |
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312 | # define EXCEPTION_INSTRUCTION_TLB 0x0a // ITLB miss |
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313 | # define EXCEPTION_RANGE 0x0b // Overflow or access at a unimplemented register or context |
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314 | # define EXCEPTION_SYSCALL 0x0c // System Call |
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315 | # define EXCEPTION_FLOATING_POINT 0x0d // Caused by a floating instruction |
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316 | # define EXCEPTION_TRAP 0x0e // L.trap or debug unit |
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317 | # define EXCEPTION_RESERVED_0 0x0f // Reserved for a futur usage |
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318 | # define EXCEPTION_RESERVED_1 0x10 // Reserved for a futur usage |
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319 | # define EXCEPTION_RESERVED_2 0x11 // Reserved for a futur usage |
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320 | # define EXCEPTION_RESERVED_3 0x12 // Reserved for a futur usage |
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321 | # define EXCEPTION_RESERVED_4 0x13 // Reserved for a futur usage |
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322 | # define EXCEPTION_RESERVED_5 0x14 // Reserved for a futur usage |
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323 | # define EXCEPTION_RESERVED_6 0x15 // Reserved for implemented specific exceptions |
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324 | # define EXCEPTION_RESERVED_7 0x16 // Reserved for implemented specific exceptions |
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325 | # define EXCEPTION_RESERVED_8 0x17 // Reserved for implemented specific exceptions |
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326 | # define EXCEPTION_RESERVED_9 0x18 // Reserved for implemented specific exceptions |
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327 | # define EXCEPTION_CUSTOM_0 0x19 // Reserved for custom exceptions |
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328 | # define EXCEPTION_CUSTOM_1 0x1a // Reserved for custom exceptions |
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329 | # define EXCEPTION_CUSTOM_2 0x1b // Reserved for custom exceptions |
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330 | # define EXCEPTION_CUSTOM_3 0x1c // Reserved for custom exceptions |
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331 | # define EXCEPTION_CUSTOM_4 0x1d // Reserved for custom exceptions |
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332 | # define EXCEPTION_CUSTOM_5 0x1e // Reserved for custom exceptions |
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333 | # define EXCEPTION_CUSTOM_6 0x1f // Reserved for custom exceptions |
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334 | |
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335 | //SR[14].EPH : Exception Prefix High |
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336 | // EPH = 0 Exceptions vectors are located in memory area starting at 0x0 |
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337 | // EPH = 1 Exception vectors are located in memory area starting at 0xF0000000 |
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338 | |
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339 | #define exception_to_address(eph,x) (((eph==0)?0x0:0xF0000000)+(x<<8)) |
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340 | |
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341 | // Exception Execution |
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342 | # define EXCEPTION_IFETCH_NONE 0x00 // Fetch Unit generate none exception |
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343 | # define EXCEPTION_IFETCH_INSTRUCTION_TLB 0x0a // ITLB miss |
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344 | # define EXCEPTION_IFETCH_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables |
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345 | # define EXCEPTION_IFETCH_BUS_ERROR 0x02 // Access at a invalid physical address |
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346 | |
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347 | # define EXCEPTION_DECOD_NONE 0x00 // none exception |
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348 | # define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION 0x01 // Instruction is illegal (no implemented) |
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349 | # define EXCEPTION_DECOD_SYSCALL 0x02 // System Call |
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350 | //#define EXCEPTION_DECOD_TRAP 0x0e // L.trap or debug unit (note : must read SR !) |
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351 | # define EXCEPTION_DECOD_INSTRUCTION_TLB 0x0a // ITLB miss |
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352 | # define EXCEPTION_DECOD_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables |
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353 | # define EXCEPTION_DECOD_BUS_ERROR 0x02 // Access at a invalid physical address |
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354 | |
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355 | // WARNING : Keep EXCEPTION_ALU_NONE value at 0x00 (kind of hard coded in functional unit's vhdl code). |
---|
356 | # define EXCEPTION_ALU_NONE 0x00 // Functionnal unit generate none exception |
---|
357 | # define EXCEPTION_ALU_RANGE 0x0b // |
---|
358 | # define EXCEPTION_ALU_SPR_ACCESS_INVALID 0x12 // * SPR present in ALU but not compatible privilege |
---|
359 | # define EXCEPTION_ALU_SPR_ACCESS_MUST_READ 0x13 // * SPR not present in ALU |
---|
360 | # define EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE 0x14 // * SPR not present in ALU |
---|
361 | |
---|
362 | # define EXCEPTION_MEMORY_NONE 0x00 // Load/Store generate none exception |
---|
363 | # define EXCEPTION_MEMORY_ALIGNMENT 0x06 // Load/Store access is not aligned |
---|
364 | # define EXCEPTION_MEMORY_DATA_TLB 0x09 // DTLB miss |
---|
365 | # define EXCEPTION_MEMORY_DATA_PAGE 0x03 // No matching or page violation protection in pages tables |
---|
366 | # define EXCEPTION_MEMORY_BUS_ERROR 0x02 // Access at a invalid physical address |
---|
367 | # define EXCEPTION_MEMORY_MISS_SPECULATION 0x10 // * Load miss speculation |
---|
368 | # define EXCEPTION_MEMORY_LOAD_SPECULATIVE 0x11 // * The load is speculative : write in register file, but don't commit |
---|
369 | |
---|
370 | # define EXCEPTION_CUSTOM_NONE 0x00 // Custom unit generate none exception |
---|
371 | # define EXCEPTION_CUSTOM_CUST_0 0x19 // Reserved for custom exceptions |
---|
372 | # define EXCEPTION_CUSTOM_CUST_1 0x1a // Reserved for custom exceptions |
---|
373 | # define EXCEPTION_CUSTOM_CUST_2 0x1b // Reserved for custom exceptions |
---|
374 | # define EXCEPTION_CUSTOM_CUST_3 0x1c // Reserved for custom exceptions |
---|
375 | # define EXCEPTION_CUSTOM_CUST_4 0x1d // Reserved for custom exceptions |
---|
376 | # define EXCEPTION_CUSTOM_CUST_5 0x1e // Reserved for custom exceptions |
---|
377 | # define EXCEPTION_CUSTOM_CUST_6 0x1f // Reserved for custom exceptions |
---|
378 | |
---|
379 | # define EXCEPTION_USE_NONE 0x00 // |
---|
380 | # define EXCEPTION_USE_ILLEGAL_INSTRUCTION 0x01 // illegal_instruction |
---|
381 | # define EXCEPTION_USE_RANGE 0x02 // range |
---|
382 | # define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT 0x03 // TLB miss, page fault, bus error, alignment |
---|
383 | # define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT 0x04 // TLB miss, page fault, bus error |
---|
384 | # define EXCEPTION_USE_SYSCALL 0x05 // syscall |
---|
385 | # define EXCEPTION_USE_TRAP 0x06 // trap |
---|
386 | # define EXCEPTION_USE_CUSTOM_0 0x07 // |
---|
387 | # define EXCEPTION_USE_CUSTOM_1 0x08 // |
---|
388 | # define EXCEPTION_USE_CUSTOM_2 0x09 // |
---|
389 | # define EXCEPTION_USE_CUSTOM_3 0x0a // |
---|
390 | # define EXCEPTION_USE_CUSTOM_4 0x0b // |
---|
391 | # define EXCEPTION_USE_CUSTOM_5 0x0c // |
---|
392 | # define EXCEPTION_USE_CUSTOM_6 0x0d // |
---|
393 | |
---|
394 | # define exception_ifetch_to_exception_decod(x) x |
---|
395 | # define exception_decod_to_exception(x) x |
---|
396 | # define exception_alu_to_exception(x) x |
---|
397 | # define exception_memory_to_exception(x) x |
---|
398 | # define exception_custom_to_exception(x) x |
---|
399 | |
---|
400 | //=======================================================[ icache ]===== |
---|
401 | |
---|
402 | //--------------------------------------------------[ icache_type ]----- |
---|
403 | |
---|
404 | # define SIZE_ICACHE_TYPE 2 |
---|
405 | |
---|
406 | # define ICACHE_TYPE_LOAD 0x0 // 0000 |
---|
407 | # define ICACHE_TYPE_LOCK 0x1 // 0001 |
---|
408 | # define ICACHE_TYPE_INVALIDATE 0x2 // 0010 |
---|
409 | # define ICACHE_TYPE_PREFETCH 0x3 // 0011 |
---|
410 | |
---|
411 | // just take the 2 less significative bits. |
---|
412 | #define operation_to_icache_type(x) (x&0x3) |
---|
413 | |
---|
414 | //-------------------------------------------------[ icache_error ]----- |
---|
415 | |
---|
416 | # define SIZE_ICACHE_ERROR 1 |
---|
417 | |
---|
418 | # define ICACHE_ERROR_NONE 0x0 |
---|
419 | # define ICACHE_ERROR_BUS_ERROR 0x1 |
---|
420 | |
---|
421 | //=======================================================[ dcache ]===== |
---|
422 | |
---|
423 | //--------------------------------------------------[ dcache_type ]----- |
---|
424 | |
---|
425 | # define SIZE_DCACHE_TYPE 4 |
---|
426 | |
---|
427 | //#define DCACHE_TYPE_ 0x0 // 0000 |
---|
428 | # define DCACHE_TYPE_LOCK 0x1 // 0001 |
---|
429 | # define DCACHE_TYPE_INVALIDATE 0x2 // 0010 |
---|
430 | # define DCACHE_TYPE_PREFETCH 0x3 // 0011 |
---|
431 | //#define DCACHE_TYPE_ 0x4 // 0100 |
---|
432 | //#define DCACHE_TYPE_ 0x5 // 0101 |
---|
433 | # define DCACHE_TYPE_FLUSH 0x6 // 0110 |
---|
434 | # define DCACHE_TYPE_SYNCHRONIZATION 0x7 // 0111 |
---|
435 | # define DCACHE_TYPE_LOAD_8 0x8 // 1000 |
---|
436 | # define DCACHE_TYPE_LOAD_16 0x9 // 1001 |
---|
437 | # define DCACHE_TYPE_LOAD_32 0xa // 1010 |
---|
438 | # define DCACHE_TYPE_LOAD_64 0xb // 1011 |
---|
439 | # define DCACHE_TYPE_STORE_8 0xc // 1100 |
---|
440 | # define DCACHE_TYPE_STORE_16 0xd // 1101 |
---|
441 | # define DCACHE_TYPE_STORE_32 0xe // 1110 |
---|
442 | # define DCACHE_TYPE_STORE_64 0xf // 1111 |
---|
443 | |
---|
444 | // just take the 4 less significative bits. |
---|
445 | #define operation_to_dcache_type(x) (x&0xf) |
---|
446 | |
---|
447 | //-------------------------------------------------[ dcache_error ]----- |
---|
448 | |
---|
449 | # define SIZE_DCACHE_ERROR 1 |
---|
450 | |
---|
451 | # define DCACHE_ERROR_NONE 0x0 |
---|
452 | # define DCACHE_ERROR_BUS_ERROR 0x1 |
---|
453 | |
---|
454 | //=================================================[ special_data ]===== |
---|
455 | |
---|
456 | # define SIZE_SPECIAL_DATA 2 |
---|
457 | |
---|
458 | // Position of flag in "rename register SR" (NOT IN "SR") |
---|
459 | # define FLAG_POSITION_F 0x0 // Conditionnal branch flag |
---|
460 | # define FLAG_POSITION_CY 0x1 // Carry was produced by last arithmetic operation |
---|
461 | # define FLAG_POSITION_OV 0x0 // Overflow occured during last arithmetic operation |
---|
462 | |
---|
463 | # define FLAG_F (1<<FLAG_POSITION_F ) // Conditionnal branch flag |
---|
464 | # define FLAG_CY (1<<FLAG_POSITION_CY) // Carry was produced by last arithmetic operation |
---|
465 | # define FLAG_OV (1<<FLAG_POSITION_OV) // Overflow occured during last arithmetic operation |
---|
466 | |
---|
467 | //==========================================================[ spr ]===== |
---|
468 | |
---|
469 | enum |
---|
470 | { |
---|
471 | GROUP_SYSTEM_AND_CONTROL, // 0 |
---|
472 | GROUP_DMMU, // 1 |
---|
473 | GROUP_IMMU, // 2 |
---|
474 | GROUP_DCACHE, // 3 |
---|
475 | GROUP_ICACHE, // 4 |
---|
476 | GROUP_MAC, // 5 |
---|
477 | GROUP_DEBUG, // 6 |
---|
478 | GROUP_PERFORMANCE_COUNTER, // 7 |
---|
479 | GROUP_POWER_MANAGEMENT, // 8 |
---|
480 | GROUP_PIC, // 9 |
---|
481 | GROUP_TICK_TIMER, // 10 |
---|
482 | GROUP_FLOATING_POINT, // 11 |
---|
483 | GROUP_RESERVED_1, // 12 |
---|
484 | GROUP_RESERVED_2, // 13 |
---|
485 | GROUP_RESERVED_3, // 14 |
---|
486 | GROUP_RESERVED_4, // 15 |
---|
487 | GROUP_RESERVED_5, // 16 |
---|
488 | GROUP_RESERVED_6, // 17 |
---|
489 | GROUP_RESERVED_7, // 18 |
---|
490 | GROUP_RESERVED_8, // 19 |
---|
491 | GROUP_RESERVED_9, // 20 |
---|
492 | GROUP_RESERVED_10, // 21 |
---|
493 | GROUP_RESERVED_11, // 22 |
---|
494 | GROUP_RESERVED_12, // 23 |
---|
495 | GROUP_CUSTOM_1, // 24 |
---|
496 | GROUP_CUSTOM_2, // 25 |
---|
497 | GROUP_CUSTOM_3, // 26 |
---|
498 | GROUP_CUSTOM_4, // 27 |
---|
499 | GROUP_CUSTOM_5, // 28 |
---|
500 | GROUP_CUSTOM_6, // 29 |
---|
501 | GROUP_CUSTOM_7, // 30 |
---|
502 | GROUP_CUSTOM_8, // 31 |
---|
503 | NB_GROUP |
---|
504 | }; |
---|
505 | |
---|
506 | # define NB_REG_GROUP_SYSTEM_AND_CONTROL 1536 |
---|
507 | # define NB_REG_GROUP_DMMU 1536 |
---|
508 | # define NB_REG_GROUP_IMMU 1536 |
---|
509 | # define NB_REG_GROUP_DCACHE 6 |
---|
510 | # define NB_REG_GROUP_ICACHE 4 |
---|
511 | # define NB_REG_GROUP_MAC 3 |
---|
512 | # define NB_REG_GROUP_DEBUG 22 |
---|
513 | # define NB_REG_GROUP_PERFORMANCE_COUNTER 16 |
---|
514 | # define NB_REG_GROUP_POWER_MANAGEMENT 1 |
---|
515 | # define NB_REG_GROUP_PIC 3 |
---|
516 | # define NB_REG_GROUP_TICK_TIMER 2 |
---|
517 | # define NB_REG_GROUP_FLOATING_POINT 0 |
---|
518 | # define NB_REG_GROUP_RESERVED_1 0 |
---|
519 | # define NB_REG_GROUP_RESERVED_2 0 |
---|
520 | # define NB_REG_GROUP_RESERVED_3 0 |
---|
521 | # define NB_REG_GROUP_RESERVED_4 0 |
---|
522 | # define NB_REG_GROUP_RESERVED_5 0 |
---|
523 | # define NB_REG_GROUP_RESERVED_6 0 |
---|
524 | # define NB_REG_GROUP_RESERVED_7 0 |
---|
525 | # define NB_REG_GROUP_RESERVED_8 0 |
---|
526 | # define NB_REG_GROUP_RESERVED_9 0 |
---|
527 | # define NB_REG_GROUP_RESERVED_10 0 |
---|
528 | # define NB_REG_GROUP_RESERVED_11 0 |
---|
529 | # define NB_REG_GROUP_RESERVED_12 0 |
---|
530 | # define NB_REG_GROUP_CUSTOM_1 0 |
---|
531 | # define NB_REG_GROUP_CUSTOM_2 0 |
---|
532 | # define NB_REG_GROUP_CUSTOM_3 0 |
---|
533 | # define NB_REG_GROUP_CUSTOM_4 0 |
---|
534 | # define NB_REG_GROUP_CUSTOM_5 0 |
---|
535 | # define NB_REG_GROUP_CUSTOM_6 0 |
---|
536 | # define NB_REG_GROUP_CUSTOM_7 0 |
---|
537 | # define NB_REG_GROUP_CUSTOM_8 0 |
---|
538 | |
---|
539 | static const uint32_t NB_REG_GROUP [] = |
---|
540 | {NB_REG_GROUP_SYSTEM_AND_CONTROL , |
---|
541 | NB_REG_GROUP_DMMU , |
---|
542 | NB_REG_GROUP_IMMU , |
---|
543 | NB_REG_GROUP_DCACHE , |
---|
544 | NB_REG_GROUP_ICACHE , |
---|
545 | NB_REG_GROUP_MAC , |
---|
546 | NB_REG_GROUP_DEBUG , |
---|
547 | NB_REG_GROUP_PERFORMANCE_COUNTER , |
---|
548 | NB_REG_GROUP_POWER_MANAGEMENT , |
---|
549 | NB_REG_GROUP_PIC , |
---|
550 | NB_REG_GROUP_TICK_TIMER , |
---|
551 | NB_REG_GROUP_FLOATING_POINT , |
---|
552 | NB_REG_GROUP_RESERVED_1 , |
---|
553 | NB_REG_GROUP_RESERVED_2 , |
---|
554 | NB_REG_GROUP_RESERVED_3 , |
---|
555 | NB_REG_GROUP_RESERVED_4 , |
---|
556 | NB_REG_GROUP_RESERVED_5 , |
---|
557 | NB_REG_GROUP_RESERVED_6 , |
---|
558 | NB_REG_GROUP_RESERVED_7 , |
---|
559 | NB_REG_GROUP_RESERVED_8 , |
---|
560 | NB_REG_GROUP_RESERVED_9 , |
---|
561 | NB_REG_GROUP_RESERVED_10 , |
---|
562 | NB_REG_GROUP_RESERVED_11 , |
---|
563 | NB_REG_GROUP_RESERVED_12 , |
---|
564 | NB_REG_GROUP_CUSTOM_1 , |
---|
565 | NB_REG_GROUP_CUSTOM_2 , |
---|
566 | NB_REG_GROUP_CUSTOM_3 , |
---|
567 | NB_REG_GROUP_CUSTOM_4 , |
---|
568 | NB_REG_GROUP_CUSTOM_5 , |
---|
569 | NB_REG_GROUP_CUSTOM_6 , |
---|
570 | NB_REG_GROUP_CUSTOM_7 , |
---|
571 | NB_REG_GROUP_CUSTOM_8 }; |
---|
572 | |
---|
573 | // GROUP_SYSTEM_AND_CONTROL |
---|
574 | # define SPR_VR 0 // Version register |
---|
575 | # define SPR_UPR 1 // Unit Present register |
---|
576 | # define SPR_CPUCFGR 2 // CPU Configuration register |
---|
577 | # define SPR_DMMUCFGR 3 // Data MMU Configuration register |
---|
578 | # define SPR_IMMUCFGR 4 // Instruction MMU Configuration register |
---|
579 | # define SPR_DCCFGR 5 // Data Cache Configuration register |
---|
580 | # define SPR_ICCFGR 6 // Instruction Cache Configuration register |
---|
581 | # define SPR_DCFGR 7 // Debug Configuration register |
---|
582 | # define SPR_PCCFGR 8 // Performance Counters Configuration register |
---|
583 | # define SPR_NPC 16 // PC mapped to SPR space (next PC) |
---|
584 | # define SPR_SR 17 // Supervision register |
---|
585 | # define SPR_PPC 18 // PC mapped to SPR space (previous PC) |
---|
586 | # define SPR_FPCSR 20 // FP Control Status register |
---|
587 | # define SPR_CID 21 // Context Id |
---|
588 | # define SPR_TID 22 // Thread Id |
---|
589 | # define SPR_TSR 23 // Thread Priority |
---|
590 | # define SPR_EPCR 32 // Exception PC register |
---|
591 | # define SPR_EEAR 48 // Exception EA register |
---|
592 | # define SPR_ESR 64 // Exception SR register |
---|
593 | # define SPR_GPR 1024 // GPRs mappted to SPR space |
---|
594 | |
---|
595 | // GROUP_DCACHE |
---|
596 | # define SPR_DCCR 0 // DC Control register |
---|
597 | # define SPR_DCBPR 1 // DC Block Prefetch register |
---|
598 | # define SPR_DCBFR 2 // DC Block Flush register |
---|
599 | # define SPR_DCBIR 3 // DC Block Invalidate register |
---|
600 | # define SPR_DCBWR 4 // DC Block Write-back register |
---|
601 | # define SPR_DCBLR 5 // DC Block Lock register |
---|
602 | |
---|
603 | // GROUP_ICACHE |
---|
604 | # define SPR_ICCR 0 // IC Control register |
---|
605 | # define SPR_ICBPR 1 // IC Block Prefetch register |
---|
606 | # define SPR_ICBIR 2 // IC Block Invalidate register |
---|
607 | # define SPR_ICBLR 3 // IC Block Lock register |
---|
608 | |
---|
609 | // GROUP_MAC |
---|
610 | # define SPR_MACLO 1 // MAC Low |
---|
611 | # define SPR_MACHI 2 // MAC High |
---|
612 | |
---|
613 | // SR RENAME |
---|
614 | # define NB_SPR_LOGIC 2 |
---|
615 | # define LOG2_NB_SPR_LOGIC 1 |
---|
616 | // SPR_LOGIC[0] = F |
---|
617 | // SPR_LOGIC[1] = Carry, Overflow |
---|
618 | # define SPR_LOGIC_SR_F 0x0 // Status register bit F (size = 1) |
---|
619 | # define SPR_LOGIC_SR_CY_OV 0x1 // Status register bit overflow and carry (size = 2) |
---|
620 | |
---|
621 | //----------------------------------------------[ spr_mode_access ]----- |
---|
622 | |
---|
623 | # define SPR_ACCESS_MODE_NONE 0x0 // 000 |
---|
624 | # define SPR_ACCESS_MODE_READ_ONLY 0x1 // 001 |
---|
625 | # define SPR_ACCESS_MODE_WRITE_ONLY 0x2 // 010 |
---|
626 | # define SPR_ACCESS_MODE_READ_WRITE 0x3 // 011 |
---|
627 | # define SPR_ACCESS_MODE_READ_ONLY_COND 0x5 // 101 special read |
---|
628 | |
---|
629 | //--------------------------------------------------------[ event ]----- |
---|
630 | # define SIZE_EVENT_STATE 2 |
---|
631 | |
---|
632 | # define EVENT_STATE_NO_EVENT 0 // no event : current case |
---|
633 | # define EVENT_STATE_EVENT 1 // Have a event : make necessary to manage the event |
---|
634 | # define EVENT_STATE_WAITEND 2 // Wait end of manage event (restaure a good context) |
---|
635 | # define EVENT_STATE_END 3 // CPU can continue |
---|
636 | |
---|
637 | # define SIZE_EVENT_TYPE 3 |
---|
638 | |
---|
639 | # define EVENT_TYPE_NONE 0 // no event |
---|
640 | # define EVENT_TYPE_BRANCH_MISS_SPECULATION 1 // miss of speculation (load or branch miss speculation) |
---|
641 | # define EVENT_TYPE_LOAD_MISS_SPECULATION 2 // miss of speculation (load or branch miss speculation) |
---|
642 | # define EVENT_TYPE_EXCEPTION 3 // exception or interruption occure |
---|
643 | //#define EVENT_TYPE_BRANCH_NO_ACCURATE 3 // branch is no accurate (old speculation is a miss) |
---|
644 | # define EVENT_TYPE_SPR_ACCESS 4 // decod a mtspr or mfspr instruction |
---|
645 | # define EVENT_TYPE_MSYNC 5 // decod a memory synchronization |
---|
646 | # define EVENT_TYPE_PSYNC 6 // decod a pipeline synchronization |
---|
647 | # define EVENT_TYPE_CSYNC 7 // decod a context synchronization |
---|
648 | |
---|
649 | //-------------------------------------------------[ branch_state ]----- |
---|
650 | # define SIZE_BRANCH_STATE 2 |
---|
651 | |
---|
652 | # define BRANCH_STATE_NONE 0x0 // 0 0 |
---|
653 | # define BRANCH_STATE_NSPEC_TAKE 0x1 // 0 1 -> incondionnal |
---|
654 | # define BRANCH_STATE_SPEC_NTAKE 0x2 // 1 0 |
---|
655 | # define BRANCH_STATE_SPEC_TAKE 0x3 // 1 1 |
---|
656 | |
---|
657 | //---------------------------------------------[ branch_condition ]----- |
---|
658 | |
---|
659 | # define SIZE_BRANCH_CONDITION 4 |
---|
660 | # define MAX_BRANCH_CONDITION (1<<SIZE_BRANCH_CONDITION) |
---|
661 | typedef enum |
---|
662 | { |
---|
663 | BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK = 0x0, // None condition (jump) |
---|
664 | BRANCH_CONDITION_NONE_WITH_WRITE_STACK = 0x8, // None condition (jump) |
---|
665 | BRANCH_CONDITION_FLAG_UNSET = 0x2, // Branch if Flag is clear |
---|
666 | BRANCH_CONDITION_FLAG_SET = 0x3, // Branch if Flag is set |
---|
667 | BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK = 0x4, // Branch if a register is read |
---|
668 | BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK = 0xc, // Branch if a register is read |
---|
669 | BRANCH_CONDITION_READ_STACK = 0xf // Branch with pop in stack pointer |
---|
670 | } branch_condition_t; |
---|
671 | |
---|
672 | # define is_branch_condition_valid(x) \ |
---|
673 | (( x == BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK ) or \ |
---|
674 | ( x == BRANCH_CONDITION_NONE_WITH_WRITE_STACK ) or \ |
---|
675 | ( x == BRANCH_CONDITION_FLAG_UNSET ) or \ |
---|
676 | ( x == BRANCH_CONDITION_FLAG_SET ) or \ |
---|
677 | ( x == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or \ |
---|
678 | ( x == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or \ |
---|
679 | ( x == BRANCH_CONDITION_READ_STACK )) |
---|
680 | |
---|
681 | |
---|
682 | /* |
---|
683 | enum |
---|
684 | { |
---|
685 | BRANCH_TYPE_SEQUENTIAL, |
---|
686 | BRANCH_TYPE_JUMP, |
---|
687 | BRANCH_TYPE_CONDITIONNAL, |
---|
688 | BRANCH_TYPE_REGISTER, |
---|
689 | BRANCH_TYPE_CALL, |
---|
690 | BRANCH_TYPE_RETURN, |
---|
691 | NB_BRANCH_TYPE |
---|
692 | }; |
---|
693 | |
---|
694 | # define branch_condition_to_type(x) \ |
---|
695 | (x == BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK )?BRANCH_TYPE_JUMP: \ |
---|
696 | ((x == BRANCH_CONDITION_NONE_WITH_WRITE_STACK )?BRANCH_TYPE_CALL: \ |
---|
697 | ((x == BRANCH_CONDITION_FLAG_UNSET )?BRANCH_TYPE_CONDITIONNAL: \ |
---|
698 | ((x == BRANCH_CONDITION_FLAG_SET )?BRANCH_TYPE_CONDITIONNAL: \ |
---|
699 | ((x == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK)?BRANCH_TYPE_REGISTER: \ |
---|
700 | ((x == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK )?BRANCH_TYPE_CALL: \ |
---|
701 | ((x == BRANCH_CONDITION_READ_STACK )?BRANCH_TYPE_RETURN:BRANCH_TYPE_SEQUENTIAL)))))); |
---|
702 | */ |
---|
703 | |
---|
704 | //--------------------------------------------------[ instruction ]----- |
---|
705 | # define NB_INSTRUCTION 213 // 92 ORBIS, 30 ORFPX (15 simple, 15 double), 91 ORVDX (38 on byte, 41 on half, 12 independant format) |
---|
706 | |
---|
707 | enum |
---|
708 | { |
---|
709 | // ORBIS |
---|
710 | INSTRUCTION_L_ADD, //0 |
---|
711 | INSTRUCTION_L_ADDC, //1 |
---|
712 | INSTRUCTION_L_ADDI, //2 |
---|
713 | INSTRUCTION_L_ADDIC, //3 |
---|
714 | INSTRUCTION_L_AND, //4 |
---|
715 | INSTRUCTION_L_ANDI, //5 |
---|
716 | INSTRUCTION_L_BF, //6 |
---|
717 | INSTRUCTION_L_BNF, //7 |
---|
718 | INSTRUCTION_L_CMOV, //8 |
---|
719 | INSTRUCTION_L_CSYNC, //9 |
---|
720 | INSTRUCTION_L_CUST1, //10 |
---|
721 | INSTRUCTION_L_CUST2, //11 |
---|
722 | INSTRUCTION_L_CUST3, //12 |
---|
723 | INSTRUCTION_L_CUST4, //13 |
---|
724 | INSTRUCTION_L_CUST5, //14 |
---|
725 | INSTRUCTION_L_CUST6, //15 |
---|
726 | INSTRUCTION_L_CUST7, //16 |
---|
727 | INSTRUCTION_L_CUST8, //17 |
---|
728 | INSTRUCTION_L_DIV, //18 |
---|
729 | INSTRUCTION_L_DIVU, //19 |
---|
730 | INSTRUCTION_L_EXTBS, //20 |
---|
731 | INSTRUCTION_L_EXTBZ, //21 |
---|
732 | INSTRUCTION_L_EXTHS, //22 |
---|
733 | INSTRUCTION_L_EXTHZ, //23 |
---|
734 | INSTRUCTION_L_EXTWS, //24 |
---|
735 | INSTRUCTION_L_EXTWZ, //25 |
---|
736 | INSTRUCTION_L_FF1, //26 |
---|
737 | INSTRUCTION_L_FL1, //27 |
---|
738 | INSTRUCTION_L_J, //28 |
---|
739 | INSTRUCTION_L_JAL, //29 |
---|
740 | INSTRUCTION_L_JALR, //30 |
---|
741 | INSTRUCTION_L_JR, //31 |
---|
742 | INSTRUCTION_L_LBS, //32 |
---|
743 | INSTRUCTION_L_LBZ, //33 |
---|
744 | INSTRUCTION_L_LD, //34 |
---|
745 | INSTRUCTION_L_LHS, //35 |
---|
746 | INSTRUCTION_L_LHZ, //36 |
---|
747 | INSTRUCTION_L_LWS, //37 |
---|
748 | INSTRUCTION_L_LWZ, //38 |
---|
749 | INSTRUCTION_L_MAC, //39 |
---|
750 | INSTRUCTION_L_MACI, //40 |
---|
751 | INSTRUCTION_L_MACRC, //41 |
---|
752 | INSTRUCTION_L_MFSPR, //42 |
---|
753 | INSTRUCTION_L_MOVHI, //43 |
---|
754 | INSTRUCTION_L_MSB, //44 |
---|
755 | INSTRUCTION_L_MSYNC, //45 |
---|
756 | INSTRUCTION_L_MTSPR, //46 |
---|
757 | INSTRUCTION_L_MUL, //47 |
---|
758 | INSTRUCTION_L_MULI, //48 |
---|
759 | INSTRUCTION_L_MULU, //49 |
---|
760 | INSTRUCTION_L_NOP, //50 |
---|
761 | INSTRUCTION_L_OR, //51 |
---|
762 | INSTRUCTION_L_ORI, //52 |
---|
763 | INSTRUCTION_L_PSYNC, //53 |
---|
764 | INSTRUCTION_L_RFE, //54 |
---|
765 | INSTRUCTION_L_ROR, //55 |
---|
766 | INSTRUCTION_L_RORI, //56 |
---|
767 | INSTRUCTION_L_SB, //57 |
---|
768 | INSTRUCTION_L_SD, //58 |
---|
769 | INSTRUCTION_L_SFEQ, //59 |
---|
770 | INSTRUCTION_L_SFEQI, //60 |
---|
771 | INSTRUCTION_L_SFGES, //61 |
---|
772 | INSTRUCTION_L_SFGESI, //62 |
---|
773 | INSTRUCTION_L_SFGEU, //63 |
---|
774 | INSTRUCTION_L_SFGEUI, //64 |
---|
775 | INSTRUCTION_L_SFGTS, //65 |
---|
776 | INSTRUCTION_L_SFGTSI, //66 |
---|
777 | INSTRUCTION_L_SFGTU, //67 |
---|
778 | INSTRUCTION_L_SFGTUI, //68 |
---|
779 | INSTRUCTION_L_SFLES, //69 |
---|
780 | INSTRUCTION_L_SFLESI, //70 |
---|
781 | INSTRUCTION_L_SFLEU, //71 |
---|
782 | INSTRUCTION_L_SFLEUI, //72 |
---|
783 | INSTRUCTION_L_SFLTS, //73 |
---|
784 | INSTRUCTION_L_SFLTSI, //74 |
---|
785 | INSTRUCTION_L_SFLTU, //75 |
---|
786 | INSTRUCTION_L_SFLTUI, //76 |
---|
787 | INSTRUCTION_L_SFNE, //77 |
---|
788 | INSTRUCTION_L_SFNEI, //78 |
---|
789 | INSTRUCTION_L_SH, //79 |
---|
790 | INSTRUCTION_L_SLL, //80 |
---|
791 | INSTRUCTION_L_SLLI, //81 |
---|
792 | INSTRUCTION_L_SRA, //82 |
---|
793 | INSTRUCTION_L_SRAI, //83 |
---|
794 | INSTRUCTION_L_SRL, //84 |
---|
795 | INSTRUCTION_L_SRLI, //85 |
---|
796 | INSTRUCTION_L_SUB, //86 |
---|
797 | INSTRUCTION_L_SW, //87 |
---|
798 | INSTRUCTION_L_SYS, //88 |
---|
799 | INSTRUCTION_L_TRAP, //89 |
---|
800 | INSTRUCTION_L_XOR, //90 |
---|
801 | INSTRUCTION_L_XORI, //91 |
---|
802 | // ORFPX |
---|
803 | INSTRUCTION_LF_ADD_D, //92 |
---|
804 | INSTRUCTION_LF_ADD_S, //93 |
---|
805 | INSTRUCTION_LF_CUST1_D, //94 |
---|
806 | INSTRUCTION_LF_CUST1_S, //95 |
---|
807 | INSTRUCTION_LF_DIV_D, //96 |
---|
808 | INSTRUCTION_LF_DIV_S, //97 |
---|
809 | INSTRUCTION_LF_FTOI_D, //98 |
---|
810 | INSTRUCTION_LF_FTOI_S, //99 |
---|
811 | INSTRUCTION_LF_ITOF_D, //100 |
---|
812 | INSTRUCTION_LF_ITOF_S, //101 |
---|
813 | INSTRUCTION_LF_MADD_D, //102 |
---|
814 | INSTRUCTION_LF_MADD_S, //103 |
---|
815 | INSTRUCTION_LF_MUL_D, //104 |
---|
816 | INSTRUCTION_LF_MUL_S, //105 |
---|
817 | INSTRUCTION_LF_REM_D, //106 |
---|
818 | INSTRUCTION_LF_REM_S, //107 |
---|
819 | INSTRUCTION_LF_SFEQ_D, //108 |
---|
820 | INSTRUCTION_LF_SFEQ_S, //109 |
---|
821 | INSTRUCTION_LF_SFGE_D, //110 |
---|
822 | INSTRUCTION_LF_SFGE_S, //111 |
---|
823 | INSTRUCTION_LF_SFGT_D, //112 |
---|
824 | INSTRUCTION_LF_SFGT_S, //113 |
---|
825 | INSTRUCTION_LF_SFLE_D, //114 |
---|
826 | INSTRUCTION_LF_SFLE_S, //115 |
---|
827 | INSTRUCTION_LF_SFLT_D, //116 |
---|
828 | INSTRUCTION_LF_SFLT_S, //117 |
---|
829 | INSTRUCTION_LF_SFNE_D, //118 |
---|
830 | INSTRUCTION_LF_SFNE_S, //119 |
---|
831 | INSTRUCTION_LF_SUB_D, //120 |
---|
832 | INSTRUCTION_LF_SUB_S, //121 |
---|
833 | // ORVDX |
---|
834 | INSTRUCTION_LV_ADD_B, //122 |
---|
835 | INSTRUCTION_LV_ADD_H, //123 |
---|
836 | INSTRUCTION_LV_ADDS_B, //124 |
---|
837 | INSTRUCTION_LV_ADDS_H, //125 |
---|
838 | INSTRUCTION_LV_ADDU_B, //126 |
---|
839 | INSTRUCTION_LV_ADDU_H, //127 |
---|
840 | INSTRUCTION_LV_ADDUS_B, //128 |
---|
841 | INSTRUCTION_LV_ADDUS_H, //129 |
---|
842 | INSTRUCTION_LV_ALL_EQ_B, //130 |
---|
843 | INSTRUCTION_LV_ALL_EQ_H, //131 |
---|
844 | INSTRUCTION_LV_ALL_GE_B, //132 |
---|
845 | INSTRUCTION_LV_ALL_GE_H, //133 |
---|
846 | INSTRUCTION_LV_ALL_GT_B, //134 |
---|
847 | INSTRUCTION_LV_ALL_GT_H, //135 |
---|
848 | INSTRUCTION_LV_ALL_LE_B, //136 |
---|
849 | INSTRUCTION_LV_ALL_LE_H, //137 |
---|
850 | INSTRUCTION_LV_ALL_LT_B, //138 |
---|
851 | INSTRUCTION_LV_ALL_LT_H, //139 |
---|
852 | INSTRUCTION_LV_ALL_NE_B, //140 |
---|
853 | INSTRUCTION_LV_ALL_NE_H, //141 |
---|
854 | INSTRUCTION_LV_AND, //142 |
---|
855 | INSTRUCTION_LV_ANY_EQ_B, //143 |
---|
856 | INSTRUCTION_LV_ANY_EQ_H, //144 |
---|
857 | INSTRUCTION_LV_ANY_GE_B, //145 |
---|
858 | INSTRUCTION_LV_ANY_GE_H, //146 |
---|
859 | INSTRUCTION_LV_ANY_GT_B, //147 |
---|
860 | INSTRUCTION_LV_ANY_GT_H, //148 |
---|
861 | INSTRUCTION_LV_ANY_LE_B, //149 |
---|
862 | INSTRUCTION_LV_ANY_LE_H, //150 |
---|
863 | INSTRUCTION_LV_ANY_LT_B, //151 |
---|
864 | INSTRUCTION_LV_ANY_LT_H, //152 |
---|
865 | INSTRUCTION_LV_ANY_NE_B, //153 |
---|
866 | INSTRUCTION_LV_ANY_NE_H, //154 |
---|
867 | INSTRUCTION_LV_AVG_B, //155 |
---|
868 | INSTRUCTION_LV_AVG_H, //156 |
---|
869 | INSTRUCTION_LV_CMP_EQ_B, //157 |
---|
870 | INSTRUCTION_LV_CMP_EQ_H, //158 |
---|
871 | INSTRUCTION_LV_CMP_GE_B, //159 |
---|
872 | INSTRUCTION_LV_CMP_GE_H, //160 |
---|
873 | INSTRUCTION_LV_CMP_GT_B, //161 |
---|
874 | INSTRUCTION_LV_CMP_GT_H, //162 |
---|
875 | INSTRUCTION_LV_CMP_LE_B, //163 |
---|
876 | INSTRUCTION_LV_CMP_LE_H, //164 |
---|
877 | INSTRUCTION_LV_CMP_LT_B, //165 |
---|
878 | INSTRUCTION_LV_CMP_LT_H, //166 |
---|
879 | INSTRUCTION_LV_CMP_NE_B, //167 |
---|
880 | INSTRUCTION_LV_CMP_NE_H, //168 |
---|
881 | INSTRUCTION_LV_CUST1, //169 |
---|
882 | INSTRUCTION_LV_CUST2, //170 |
---|
883 | INSTRUCTION_LV_CUST3, //171 |
---|
884 | INSTRUCTION_LV_CUST4, //172 |
---|
885 | INSTRUCTION_LV_MADDS_H, //173 |
---|
886 | INSTRUCTION_LV_MAX_B, //174 |
---|
887 | INSTRUCTION_LV_MAX_H, //175 |
---|
888 | INSTRUCTION_LV_MERGE_B, //176 |
---|
889 | INSTRUCTION_LV_MERGE_H, //177 |
---|
890 | INSTRUCTION_LV_MIN_B, //178 |
---|
891 | INSTRUCTION_LV_MIN_H, //179 |
---|
892 | INSTRUCTION_LV_MSUBS_H, //180 |
---|
893 | INSTRUCTION_LV_MULS_H, //181 |
---|
894 | INSTRUCTION_LV_NAND, //182 |
---|
895 | INSTRUCTION_LV_NOR, //183 |
---|
896 | INSTRUCTION_LV_OR, //184 |
---|
897 | INSTRUCTION_LV_PACK_B, //185 |
---|
898 | INSTRUCTION_LV_PACK_H, //186 |
---|
899 | INSTRUCTION_LV_PACKS_B, //187 |
---|
900 | INSTRUCTION_LV_PACKS_H, //188 |
---|
901 | INSTRUCTION_LV_PACKUS_B, //189 |
---|
902 | INSTRUCTION_LV_PACKUS_H, //290 |
---|
903 | INSTRUCTION_LV_PERM_N, //291 |
---|
904 | INSTRUCTION_LV_RL_B, //292 |
---|
905 | INSTRUCTION_LV_RL_H, //293 |
---|
906 | INSTRUCTION_LV_SLL, //294 |
---|
907 | INSTRUCTION_LV_SLL_B, //295 |
---|
908 | INSTRUCTION_LV_SLL_H, //296 |
---|
909 | INSTRUCTION_LV_SRA_B, //297 |
---|
910 | INSTRUCTION_LV_SRA_H, //298 |
---|
911 | INSTRUCTION_LV_SRL, //299 |
---|
912 | INSTRUCTION_LV_SRL_B, //200 |
---|
913 | INSTRUCTION_LV_SRL_H, //201 |
---|
914 | INSTRUCTION_LV_SUB_B, //202 |
---|
915 | INSTRUCTION_LV_SUB_H, //203 |
---|
916 | INSTRUCTION_LV_SUBS_B, //204 |
---|
917 | INSTRUCTION_LV_SUBS_H, //205 |
---|
918 | INSTRUCTION_LV_SUBU_B, //206 |
---|
919 | INSTRUCTION_LV_SUBU_H, //207 |
---|
920 | INSTRUCTION_LV_SUBUS_B, //208 |
---|
921 | INSTRUCTION_LV_SUBUS_H, //209 |
---|
922 | INSTRUCTION_LV_UNPACK_B, //210 |
---|
923 | INSTRUCTION_LV_UNPACK_H, //211 |
---|
924 | INSTRUCTION_LV_XOR //212 |
---|
925 | }; |
---|
926 | |
---|
927 | //-----------------------------------------------[ Code Operation ]----- |
---|
928 | |
---|
929 | # define MAX_OPCOD_0 64 // Instructions with immediat |
---|
930 | # define MAX_OPCOD_1 64 // Instruction ORFPX32/64 |
---|
931 | # define MAX_OPCOD_2 256 // Instruction ORVDX64 |
---|
932 | # define MAX_OPCOD_3 256 // Instructions Register-Register |
---|
933 | # define MAX_OPCOD_4 32 // Instructions "set flag" with register |
---|
934 | # define MAX_OPCOD_5 32 // Instructions "set flag" with immediat |
---|
935 | # define MAX_OPCOD_6 4 // Instruction Shift/Rotate with immediat |
---|
936 | # define MAX_OPCOD_7 16 // Instructions multiply with HI-LO |
---|
937 | # define MAX_OPCOD_8 2 // Instructions acces at HI-LO |
---|
938 | # define MAX_OPCOD_9 8 // Instructions special |
---|
939 | # define MAX_OPCOD_10 4 // Instructions no operation |
---|
940 | # define MAX_OPCOD_11 4 // Instruction Shift/Rotate with register |
---|
941 | # define MAX_OPCOD_12 4 // Instructions extend |
---|
942 | # define MAX_OPCOD_13 4 // Instructions extend (64b) |
---|
943 | |
---|
944 | // OPCOD_0 - [31:26] Instructions with immediat |
---|
945 | # define OPCOD_L_J 0x00 // 000_000 |
---|
946 | # define OPCOD_L_JAL 0x01 // 000_001 |
---|
947 | # define OPCOD_L_BNF 0x03 // 000_011 |
---|
948 | # define OPCOD_L_BF 0x04 // 000_100 |
---|
949 | # define OPCOD_L_RFE 0x09 // 001_001 |
---|
950 | # define OPCOD_L_JR 0x11 // 010_001 |
---|
951 | # define OPCOD_L_JALR 0x12 // 010_010 |
---|
952 | # define OPCOD_L_MACI 0x13 // 010_011 |
---|
953 | # define OPCOD_L_CUST1 0x1c // 011_100 |
---|
954 | # define OPCOD_L_CUST2 0x1d // 011_101 |
---|
955 | # define OPCOD_L_CUST3 0x1e // 011_110 |
---|
956 | # define OPCOD_L_CUST4 0x1f // 011_111 |
---|
957 | # define OPCOD_L_CUST5 0x3c // 111_100 |
---|
958 | # define OPCOD_L_CUST6 0x3d // 111_101 |
---|
959 | # define OPCOD_L_CUST7 0x3e // 111_110 |
---|
960 | # define OPCOD_L_CUST8 0x3f // 111_111 |
---|
961 | # define OPCOD_L_LD 0x20 // 100_000 |
---|
962 | # define OPCOD_L_LWZ 0x21 // 100_001 |
---|
963 | # define OPCOD_L_LWS 0x22 // 100_010 |
---|
964 | # define OPCOD_L_LBZ 0x23 // 100_011 |
---|
965 | # define OPCOD_L_LBS 0x24 // 100_100 |
---|
966 | # define OPCOD_L_LHZ 0x25 // 100_101 |
---|
967 | # define OPCOD_L_LHS 0x26 // 100_110 |
---|
968 | # define OPCOD_L_ADDI 0x27 // 100_111 |
---|
969 | # define OPCOD_L_ADDIC 0x28 // 101_000 |
---|
970 | # define OPCOD_L_ANDI 0x29 // 101_001 |
---|
971 | # define OPCOD_L_ORI 0x2a // 101_010 |
---|
972 | # define OPCOD_L_XORI 0x2b // 101_011 |
---|
973 | # define OPCOD_L_MULI 0x2c // 101_100 |
---|
974 | # define OPCOD_L_MFSPR 0x2d // 101_101 |
---|
975 | # define OPCOD_L_MTSPR 0x30 // 110_000 |
---|
976 | # define OPCOD_L_SD 0x34 // 110_100 |
---|
977 | # define OPCOD_L_SW 0x35 // 110_101 |
---|
978 | # define OPCOD_L_SB 0x36 // 110_110 |
---|
979 | # define OPCOD_L_SH 0x37 // 110_111 |
---|
980 | |
---|
981 | # define OPCOD_1 0x33 // 110_011 // Instruction ORFPX32/64 |
---|
982 | # define OPCOD_2 0x0a // 001_010 // Instruction ORVDX64 |
---|
983 | # define OPCOD_3 0x38 // 111_000 // Instructions Register-Register |
---|
984 | # define OPCOD_4 0x39 // 111_001 // Instructions "set flag" with register |
---|
985 | # define OPCOD_5 0x2f // 101_111 // Instructions "set flag" with immediat |
---|
986 | # define OPCOD_6 0x2e // 101_110 // Instruction Shift/Rotate with immediat |
---|
987 | # define OPCOD_7 0x31 // 110_001 // Instructions multiply with HI-LO |
---|
988 | # define OPCOD_8 0x06 // 000_110 // Instructions acces at HI-LO |
---|
989 | # define OPCOD_9 0x08 // 001_000 // Instructions special |
---|
990 | # define OPCOD_10 0x05 // 000_101 // Instructions no operation |
---|
991 | |
---|
992 | // OPCOD_3 instructions - [9:8] [3:0] Instructions Register-Register |
---|
993 | # define OPCOD_L_ADD 0x00 // 00_0000 |
---|
994 | # define OPCOD_L_ADDC 0x01 // 00_0001 |
---|
995 | # define OPCOD_L_SUB 0x02 // 00_0010 |
---|
996 | # define OPCOD_L_AND 0x03 // 00_0011 |
---|
997 | # define OPCOD_L_OR 0x04 // 00_0100 |
---|
998 | # define OPCOD_L_XOR 0x05 // 00_0101 |
---|
999 | # define OPCOD_L_CMOV 0x0e // 00_1110 |
---|
1000 | # define OPCOD_L_FF1 0x0f // 00_1111 |
---|
1001 | # define OPCOD_L_FL1 0x1f // 01_1111 |
---|
1002 | # define OPCOD_L_MUL 0x36 // 11_0110 |
---|
1003 | # define OPCOD_L_DIV 0x39 // 11_1001 |
---|
1004 | # define OPCOD_L_DIVU 0x3a // 11_1010 |
---|
1005 | # define OPCOD_L_MULU 0x3b // 11_1011 |
---|
1006 | |
---|
1007 | # define OPCOD_11 0x8 // 1000 // Instruction Shift/Rotate with register |
---|
1008 | # define OPCOD_12 0xc // 1100 // Instructions extend |
---|
1009 | # define OPCOD_13 0xd // 1101 // Instructions extend (64b) |
---|
1010 | |
---|
1011 | // OPCOD_4 instructions - [25:21] Instructions "set flag" with register |
---|
1012 | # define OPCOD_L_SFEQ 0x00 // 00000 |
---|
1013 | # define OPCOD_L_SFNE 0x01 // 00001 |
---|
1014 | # define OPCOD_L_SFGTU 0x02 // 00010 |
---|
1015 | # define OPCOD_L_SFGEU 0x03 // 00011 |
---|
1016 | # define OPCOD_L_SFLTU 0x04 // 00100 |
---|
1017 | # define OPCOD_L_SFLEU 0x05 // 00101 |
---|
1018 | # define OPCOD_L_SFGTS 0x0a // 01010 |
---|
1019 | # define OPCOD_L_SFGES 0x0b // 01011 |
---|
1020 | # define OPCOD_L_SFLTS 0x0c // 01100 |
---|
1021 | # define OPCOD_L_SFLES 0x0d // 01101 |
---|
1022 | |
---|
1023 | // OPCOD_5 instructions - [25:21] Instructions "set flag" with immediat |
---|
1024 | # define OPCOD_L_SFEQI 0x00 // 00000 |
---|
1025 | # define OPCOD_L_SFNEI 0x01 // 00001 |
---|
1026 | # define OPCOD_L_SFGTUI 0x02 // 00010 |
---|
1027 | # define OPCOD_L_SFGEUI 0x03 // 00011 |
---|
1028 | # define OPCOD_L_SFLTUI 0x04 // 00100 |
---|
1029 | # define OPCOD_L_SFLEUI 0x05 // 00101 |
---|
1030 | # define OPCOD_L_SFGTSI 0x0a // 01010 |
---|
1031 | # define OPCOD_L_SFGESI 0x0b // 01011 |
---|
1032 | # define OPCOD_L_SFLTSI 0x0c // 01100 |
---|
1033 | # define OPCOD_L_SFLESI 0x0d // 01101 |
---|
1034 | |
---|
1035 | // OPCOD_6 instructions - [7:6] Instruction Shift/Rotate with immediat |
---|
1036 | # define OPCOD_L_SLLI 0x0 // 00 |
---|
1037 | # define OPCOD_L_SRLI 0x1 // 01 |
---|
1038 | # define OPCOD_L_SRAI 0x2 // 10 |
---|
1039 | # define OPCOD_L_RORI 0x3 // 11 |
---|
1040 | |
---|
1041 | // OPCOD_7 instructions - [3:0] Instructions multiply with HI-LO |
---|
1042 | # define OPCOD_L_MAC 0x1 // 0001 |
---|
1043 | # define OPCOD_L_MSB 0x2 // 0010 |
---|
1044 | |
---|
1045 | // OPCOD_8 instructions - [17] Instructions acces at HI-LO |
---|
1046 | # define OPCOD_L_MOVHI 0x0 // 0 |
---|
1047 | # define OPCOD_L_MACRC 0x1 // 1 |
---|
1048 | |
---|
1049 | // OPCOD_9 instructions - [25:23] Instruction special |
---|
1050 | # define OPCOD_L_SYS 0x0 // 000 |
---|
1051 | # define OPCOD_L_TRAP 0x2 // 010 |
---|
1052 | # define OPCOD_L_MSYNC 0x4 // 100 |
---|
1053 | # define OPCOD_L_PSYNC 0x5 // 101 |
---|
1054 | # define OPCOD_L_CSYNC 0x6 // 110 |
---|
1055 | |
---|
1056 | // OPCOD_10 instructions - [25:24] Instruction no operation |
---|
1057 | # define OPCOD_L_NOP 0x1 // 01 |
---|
1058 | |
---|
1059 | // OPCOD_11 instructions - [7:6] Instruction Shift/Rotate with register |
---|
1060 | # define OPCOD_L_SLL 0x0 // 00 |
---|
1061 | # define OPCOD_L_SRL 0x1 // 01 |
---|
1062 | # define OPCOD_L_SRA 0x2 // 10 |
---|
1063 | # define OPCOD_L_ROR 0x3 // 11 |
---|
1064 | |
---|
1065 | // OPCOD_12 instructions - [9:6] Instructions extend |
---|
1066 | # define OPCOD_L_EXTHS 0x0 // 0000 |
---|
1067 | # define OPCOD_L_EXTHZ 0x2 // 0010 |
---|
1068 | # define OPCOD_L_EXTBS 0x1 // 0001 |
---|
1069 | # define OPCOD_L_EXTBZ 0x3 // 0011 |
---|
1070 | |
---|
1071 | // OPCOD_13 instructions - [9:6] Instructions extend (64b) |
---|
1072 | # define OPCOD_L_EXTWS 0x0 // 0000 |
---|
1073 | # define OPCOD_L_EXTWZ 0x1 // 0001 |
---|
1074 | |
---|
1075 | }; // end namespace behavioural |
---|
1076 | |
---|
1077 | template<> inline std::string toString<morpheo::behavioural::type_t>(const morpheo::behavioural::type_t& x) |
---|
1078 | { |
---|
1079 | switch (x) |
---|
1080 | { |
---|
1081 | case morpheo::behavioural::TYPE_ALU : return "ALU" ; |
---|
1082 | case morpheo::behavioural::TYPE_SHIFT : return "SHIFT" ; |
---|
1083 | case morpheo::behavioural::TYPE_MOVE : return "MOVE" ; |
---|
1084 | case morpheo::behavioural::TYPE_TEST : return "TEST" ; |
---|
1085 | case morpheo::behavioural::TYPE_MUL : return "MUL" ; |
---|
1086 | case morpheo::behavioural::TYPE_DIV : return "DIV" ; |
---|
1087 | case morpheo::behavioural::TYPE_EXTEND : return "EXTEND" ; |
---|
1088 | case morpheo::behavioural::TYPE_FIND : return "FIND" ; |
---|
1089 | case morpheo::behavioural::TYPE_SPECIAL : return "SPECIAL" ; |
---|
1090 | case morpheo::behavioural::TYPE_CUSTOM : return "CUSTOM" ; |
---|
1091 | case morpheo::behavioural::TYPE_BRANCH : return "BRANCH" ; |
---|
1092 | case morpheo::behavioural::TYPE_MEMORY : return "MEMORY" ; |
---|
1093 | default : return ""; |
---|
1094 | } |
---|
1095 | }; |
---|
1096 | |
---|
1097 | template<> inline std::string toString<morpheo::behavioural::branch_condition_t>(const morpheo::behavioural::branch_condition_t& x) |
---|
1098 | { |
---|
1099 | switch (x) |
---|
1100 | { |
---|
1101 | case morpheo::behavioural::BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK : return "none_without_write_stack" ; |
---|
1102 | case morpheo::behavioural::BRANCH_CONDITION_NONE_WITH_WRITE_STACK : return "none_with_write_stack" ; |
---|
1103 | case morpheo::behavioural::BRANCH_CONDITION_FLAG_UNSET : return "flag_unset" ; |
---|
1104 | case morpheo::behavioural::BRANCH_CONDITION_FLAG_SET : return "flag_set" ; |
---|
1105 | case morpheo::behavioural::BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK : return "read_register_without_write_stack"; |
---|
1106 | case morpheo::behavioural::BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK : return "read_register_with_write_stack" ; |
---|
1107 | case morpheo::behavioural::BRANCH_CONDITION_READ_STACK : return "read_stack" ; |
---|
1108 | default : return ""; |
---|
1109 | } |
---|
1110 | }; |
---|
1111 | |
---|
1112 | // template<> inline std::string toString<morpheo::behavioural::event_state_t>(const morpheo::behavioural::event_state_t& x) |
---|
1113 | // { |
---|
1114 | // switch (x) |
---|
1115 | // { |
---|
1116 | // case morpheo::behavioural::EVENT_STATE_NO_EVENT : return "EVENT_STATE_NO_EVENT"; |
---|
1117 | // case morpheo::behavioural::EVENT_STATE_EVENT : return "EVENT_STATE_EVENT" ; |
---|
1118 | // case morpheo::behavioural::EVENT_STATE_WAITEND : return "EVENT_STATE_WAITEND" ; |
---|
1119 | // case morpheo::behavioural::EVENT_STATE_END : return "EVENT_STATE_END" ; |
---|
1120 | // default : return ""; |
---|
1121 | // } |
---|
1122 | // }; |
---|
1123 | |
---|
1124 | // template<> inline std::string toString<morpheo::behavioural::event_type_t>(const morpheo::behavioural::event_type_t& x) |
---|
1125 | // { |
---|
1126 | // switch (x) |
---|
1127 | // { |
---|
1128 | // case morpheo::behavioural::EVENT_TYPE_NONE : return "EVENT_TYPE_NONE" ; |
---|
1129 | // case morpheo::behavioural::EVENT_TYPE_MISS_SPECULATION : return "EVENT_TYPE_MISS_SPECULATION" ; |
---|
1130 | // case morpheo::behavioural::EVENT_TYPE_EXCEPTION : return "EVENT_TYPE_EXCEPTION" ; |
---|
1131 | // case morpheo::behavioural::EVENT_TYPE_BRANCH_NO_ACCURATE : return "EVENT_TYPE_BRANCH_NO_ACCURATE"; |
---|
1132 | // case morpheo::behavioural::EVENT_TYPE_SPR_ACCESS : return "EVENT_TYPE_SPR_ACCESS" ; |
---|
1133 | // case morpheo::behavioural::EVENT_TYPE_MSYNC : return "EVENT_TYPE_MSYNC" ; |
---|
1134 | // case morpheo::behavioural::EVENT_TYPE_PSYNC : return "EVENT_TYPE_PSYNC" ; |
---|
1135 | // case morpheo::behavioural::EVENT_TYPE_CSYNC : return "EVENT_TYPE_CSYNC" ; |
---|
1136 | // default : return ""; |
---|
1137 | // } |
---|
1138 | // }; |
---|
1139 | |
---|
1140 | inline std::string toString_instruction(const uint32_t& x) |
---|
1141 | { |
---|
1142 | switch (x) |
---|
1143 | { |
---|
1144 | // ORBIS |
---|
1145 | case morpheo::behavioural::INSTRUCTION_L_ADD : return "l.add"; |
---|
1146 | case morpheo::behavioural::INSTRUCTION_L_ADDC : return "l.addc"; |
---|
1147 | case morpheo::behavioural::INSTRUCTION_L_ADDI : return "l.addi"; |
---|
1148 | case morpheo::behavioural::INSTRUCTION_L_ADDIC : return "l.addic"; |
---|
1149 | case morpheo::behavioural::INSTRUCTION_L_AND : return "l.and"; |
---|
1150 | case morpheo::behavioural::INSTRUCTION_L_ANDI : return "l.andi"; |
---|
1151 | case morpheo::behavioural::INSTRUCTION_L_BF : return "l.bf"; |
---|
1152 | case morpheo::behavioural::INSTRUCTION_L_BNF : return "l.bnf"; |
---|
1153 | case morpheo::behavioural::INSTRUCTION_L_CMOV : return "l.cmov"; |
---|
1154 | case morpheo::behavioural::INSTRUCTION_L_CSYNC : return "l.csync"; |
---|
1155 | case morpheo::behavioural::INSTRUCTION_L_CUST1 : return "l.cust1"; |
---|
1156 | case morpheo::behavioural::INSTRUCTION_L_CUST2 : return "l.cust2"; |
---|
1157 | case morpheo::behavioural::INSTRUCTION_L_CUST3 : return "l.cust3"; |
---|
1158 | case morpheo::behavioural::INSTRUCTION_L_CUST4 : return "l.cust4"; |
---|
1159 | case morpheo::behavioural::INSTRUCTION_L_CUST5 : return "l.cust5"; |
---|
1160 | case morpheo::behavioural::INSTRUCTION_L_CUST6 : return "l.cust6"; |
---|
1161 | case morpheo::behavioural::INSTRUCTION_L_CUST7 : return "l.cust7"; |
---|
1162 | case morpheo::behavioural::INSTRUCTION_L_CUST8 : return "l.cust8"; |
---|
1163 | case morpheo::behavioural::INSTRUCTION_L_DIV : return "l.div"; |
---|
1164 | case morpheo::behavioural::INSTRUCTION_L_DIVU : return "l.divu"; |
---|
1165 | case morpheo::behavioural::INSTRUCTION_L_EXTBS : return "l.extbs"; |
---|
1166 | case morpheo::behavioural::INSTRUCTION_L_EXTBZ : return "l.extbz"; |
---|
1167 | case morpheo::behavioural::INSTRUCTION_L_EXTHS : return "l.exths"; |
---|
1168 | case morpheo::behavioural::INSTRUCTION_L_EXTHZ : return "l.exthz"; |
---|
1169 | case morpheo::behavioural::INSTRUCTION_L_EXTWS : return "l.extws"; |
---|
1170 | case morpheo::behavioural::INSTRUCTION_L_EXTWZ : return "l.extwz"; |
---|
1171 | case morpheo::behavioural::INSTRUCTION_L_FF1 : return "l.ff1"; |
---|
1172 | case morpheo::behavioural::INSTRUCTION_L_FL1 : return "l.fl1"; |
---|
1173 | case morpheo::behavioural::INSTRUCTION_L_J : return "l.j"; |
---|
1174 | case morpheo::behavioural::INSTRUCTION_L_JAL : return "l.jal"; |
---|
1175 | case morpheo::behavioural::INSTRUCTION_L_JALR : return "l.jalr"; |
---|
1176 | case morpheo::behavioural::INSTRUCTION_L_JR : return "l.jr"; |
---|
1177 | case morpheo::behavioural::INSTRUCTION_L_LBS : return "l.lbs"; |
---|
1178 | case morpheo::behavioural::INSTRUCTION_L_LBZ : return "l.lbz"; |
---|
1179 | case morpheo::behavioural::INSTRUCTION_L_LD : return "l.ld"; |
---|
1180 | case morpheo::behavioural::INSTRUCTION_L_LHS : return "l.lhs"; |
---|
1181 | case morpheo::behavioural::INSTRUCTION_L_LHZ : return "l.lhz"; |
---|
1182 | case morpheo::behavioural::INSTRUCTION_L_LWS : return "l.lws"; |
---|
1183 | case morpheo::behavioural::INSTRUCTION_L_LWZ : return "l.lwz"; |
---|
1184 | case morpheo::behavioural::INSTRUCTION_L_MAC : return "l.mac"; |
---|
1185 | case morpheo::behavioural::INSTRUCTION_L_MACI : return "l.maci"; |
---|
1186 | case morpheo::behavioural::INSTRUCTION_L_MACRC : return "l.macrc"; |
---|
1187 | case morpheo::behavioural::INSTRUCTION_L_MFSPR : return "l.mfspr"; |
---|
1188 | case morpheo::behavioural::INSTRUCTION_L_MOVHI : return "l.movhi"; |
---|
1189 | case morpheo::behavioural::INSTRUCTION_L_MSB : return "l.msb"; |
---|
1190 | case morpheo::behavioural::INSTRUCTION_L_MSYNC : return "l.msync"; |
---|
1191 | case morpheo::behavioural::INSTRUCTION_L_MTSPR : return "l.mtspr"; |
---|
1192 | case morpheo::behavioural::INSTRUCTION_L_MUL : return "l.mul"; |
---|
1193 | case morpheo::behavioural::INSTRUCTION_L_MULI : return "l.muli"; |
---|
1194 | case morpheo::behavioural::INSTRUCTION_L_MULU : return "l.mulu"; |
---|
1195 | case morpheo::behavioural::INSTRUCTION_L_NOP : return "l.nop"; |
---|
1196 | case morpheo::behavioural::INSTRUCTION_L_OR : return "l.or"; |
---|
1197 | case morpheo::behavioural::INSTRUCTION_L_ORI : return "l.ori"; |
---|
1198 | case morpheo::behavioural::INSTRUCTION_L_PSYNC : return "l.psync"; |
---|
1199 | case morpheo::behavioural::INSTRUCTION_L_RFE : return "l.rfe"; |
---|
1200 | case morpheo::behavioural::INSTRUCTION_L_ROR : return "l.ror"; |
---|
1201 | case morpheo::behavioural::INSTRUCTION_L_RORI : return "l.rori"; |
---|
1202 | case morpheo::behavioural::INSTRUCTION_L_SB : return "l.sb"; |
---|
1203 | case morpheo::behavioural::INSTRUCTION_L_SD : return "l.sd"; |
---|
1204 | case morpheo::behavioural::INSTRUCTION_L_SFEQ : return "l.sfeq"; |
---|
1205 | case morpheo::behavioural::INSTRUCTION_L_SFEQI : return "l.sfeqi"; |
---|
1206 | case morpheo::behavioural::INSTRUCTION_L_SFGES : return "l.sfges"; |
---|
1207 | case morpheo::behavioural::INSTRUCTION_L_SFGESI : return "l.sfgesi"; |
---|
1208 | case morpheo::behavioural::INSTRUCTION_L_SFGEU : return "l.sfgeu"; |
---|
1209 | case morpheo::behavioural::INSTRUCTION_L_SFGEUI : return "l.sfgeui"; |
---|
1210 | case morpheo::behavioural::INSTRUCTION_L_SFGTS : return "l.sfgts"; |
---|
1211 | case morpheo::behavioural::INSTRUCTION_L_SFGTSI : return "l.sfgtsi"; |
---|
1212 | case morpheo::behavioural::INSTRUCTION_L_SFGTU : return "l.sfgtu"; |
---|
1213 | case morpheo::behavioural::INSTRUCTION_L_SFGTUI : return "l.sfgtui"; |
---|
1214 | case morpheo::behavioural::INSTRUCTION_L_SFLES : return "l.sfles"; |
---|
1215 | case morpheo::behavioural::INSTRUCTION_L_SFLESI : return "l.sflesi"; |
---|
1216 | case morpheo::behavioural::INSTRUCTION_L_SFLEU : return "l.sfleu"; |
---|
1217 | case morpheo::behavioural::INSTRUCTION_L_SFLEUI : return "l.sfleui"; |
---|
1218 | case morpheo::behavioural::INSTRUCTION_L_SFLTS : return "l.sflts"; |
---|
1219 | case morpheo::behavioural::INSTRUCTION_L_SFLTSI : return "l.sfltsi"; |
---|
1220 | case morpheo::behavioural::INSTRUCTION_L_SFLTU : return "l.sfltu"; |
---|
1221 | case morpheo::behavioural::INSTRUCTION_L_SFLTUI : return "l.sfltui"; |
---|
1222 | case morpheo::behavioural::INSTRUCTION_L_SFNE : return "l.sfne"; |
---|
1223 | case morpheo::behavioural::INSTRUCTION_L_SFNEI : return "l.sfnei"; |
---|
1224 | case morpheo::behavioural::INSTRUCTION_L_SH : return "l.sh"; |
---|
1225 | case morpheo::behavioural::INSTRUCTION_L_SLL : return "l.sll"; |
---|
1226 | case morpheo::behavioural::INSTRUCTION_L_SLLI : return "l.slli"; |
---|
1227 | case morpheo::behavioural::INSTRUCTION_L_SRA : return "l.sra"; |
---|
1228 | case morpheo::behavioural::INSTRUCTION_L_SRAI : return "l.srai"; |
---|
1229 | case morpheo::behavioural::INSTRUCTION_L_SRL : return "l.srl"; |
---|
1230 | case morpheo::behavioural::INSTRUCTION_L_SRLI : return "l.srli"; |
---|
1231 | case morpheo::behavioural::INSTRUCTION_L_SUB : return "l.sub"; |
---|
1232 | case morpheo::behavioural::INSTRUCTION_L_SW : return "l.sw"; |
---|
1233 | case morpheo::behavioural::INSTRUCTION_L_SYS : return "l.sys"; |
---|
1234 | case morpheo::behavioural::INSTRUCTION_L_TRAP : return "l.trap"; |
---|
1235 | case morpheo::behavioural::INSTRUCTION_L_XOR : return "l.xor"; |
---|
1236 | case morpheo::behavioural::INSTRUCTION_L_XORI : return "l.xori"; |
---|
1237 | // ORFPX |
---|
1238 | case morpheo::behavioural::INSTRUCTION_LF_ADD_D : return "lf.add_d"; |
---|
1239 | case morpheo::behavioural::INSTRUCTION_LF_ADD_S : return "lf.add_s"; |
---|
1240 | case morpheo::behavioural::INSTRUCTION_LF_CUST1_D : return "lf.cust1_d"; |
---|
1241 | case morpheo::behavioural::INSTRUCTION_LF_CUST1_S : return "lf.cust1_s"; |
---|
1242 | case morpheo::behavioural::INSTRUCTION_LF_DIV_D : return "lf.div_d"; |
---|
1243 | case morpheo::behavioural::INSTRUCTION_LF_DIV_S : return "lf.div_s"; |
---|
1244 | case morpheo::behavioural::INSTRUCTION_LF_FTOI_D : return "lf.ftoi_d"; |
---|
1245 | case morpheo::behavioural::INSTRUCTION_LF_FTOI_S : return "lf.ftoi_s"; |
---|
1246 | case morpheo::behavioural::INSTRUCTION_LF_ITOF_D : return "lf.itof_d"; |
---|
1247 | case morpheo::behavioural::INSTRUCTION_LF_ITOF_S : return "lf.itof_s"; |
---|
1248 | case morpheo::behavioural::INSTRUCTION_LF_MADD_D : return "lf.madd_d"; |
---|
1249 | case morpheo::behavioural::INSTRUCTION_LF_MADD_S : return "lf.madd_s"; |
---|
1250 | case morpheo::behavioural::INSTRUCTION_LF_MUL_D : return "lf.mul_d"; |
---|
1251 | case morpheo::behavioural::INSTRUCTION_LF_MUL_S : return "lf.mul_s"; |
---|
1252 | case morpheo::behavioural::INSTRUCTION_LF_REM_D : return "lf.rem_d"; |
---|
1253 | case morpheo::behavioural::INSTRUCTION_LF_REM_S : return "lf.rem_s"; |
---|
1254 | case morpheo::behavioural::INSTRUCTION_LF_SFEQ_D : return "lf.sfeq_d"; |
---|
1255 | case morpheo::behavioural::INSTRUCTION_LF_SFEQ_S : return "lf.sfeq_s"; |
---|
1256 | case morpheo::behavioural::INSTRUCTION_LF_SFGE_D : return "lf.sfge_d"; |
---|
1257 | case morpheo::behavioural::INSTRUCTION_LF_SFGE_S : return "lf.sfge_s"; |
---|
1258 | case morpheo::behavioural::INSTRUCTION_LF_SFGT_D : return "lf.sfgt_d"; |
---|
1259 | case morpheo::behavioural::INSTRUCTION_LF_SFGT_S : return "lf.sfgt_s"; |
---|
1260 | case morpheo::behavioural::INSTRUCTION_LF_SFLE_D : return "lf.sfle_d"; |
---|
1261 | case morpheo::behavioural::INSTRUCTION_LF_SFLE_S : return "lf.sfle_s"; |
---|
1262 | case morpheo::behavioural::INSTRUCTION_LF_SFLT_D : return "lf.sflt_d"; |
---|
1263 | case morpheo::behavioural::INSTRUCTION_LF_SFLT_S : return "lf.sflt_s"; |
---|
1264 | case morpheo::behavioural::INSTRUCTION_LF_SFNE_D : return "lf.sfne_d"; |
---|
1265 | case morpheo::behavioural::INSTRUCTION_LF_SFNE_S : return "lf.sfne_s"; |
---|
1266 | case morpheo::behavioural::INSTRUCTION_LF_SUB_D : return "lf.sub_d"; |
---|
1267 | case morpheo::behavioural::INSTRUCTION_LF_SUB_S : return "lf.sub_s"; |
---|
1268 | // ORVDX |
---|
1269 | case morpheo::behavioural::INSTRUCTION_LV_ADD_B : return "lv.add_b"; |
---|
1270 | case morpheo::behavioural::INSTRUCTION_LV_ADD_H : return "lv.add_h"; |
---|
1271 | case morpheo::behavioural::INSTRUCTION_LV_ADDS_B : return "lv.adds_b"; |
---|
1272 | case morpheo::behavioural::INSTRUCTION_LV_ADDS_H : return "lv.adds_h"; |
---|
1273 | case morpheo::behavioural::INSTRUCTION_LV_ADDU_B : return "lv.addu_b"; |
---|
1274 | case morpheo::behavioural::INSTRUCTION_LV_ADDU_H : return "lv.addu_h"; |
---|
1275 | case morpheo::behavioural::INSTRUCTION_LV_ADDUS_B : return "lv.addus_b"; |
---|
1276 | case morpheo::behavioural::INSTRUCTION_LV_ADDUS_H : return "lv.addus_h"; |
---|
1277 | case morpheo::behavioural::INSTRUCTION_LV_ALL_EQ_B : return "lv.all_eq_b"; |
---|
1278 | case morpheo::behavioural::INSTRUCTION_LV_ALL_EQ_H : return "lv.all_eq_h"; |
---|
1279 | case morpheo::behavioural::INSTRUCTION_LV_ALL_GE_B : return "lv.all_ge_b"; |
---|
1280 | case morpheo::behavioural::INSTRUCTION_LV_ALL_GE_H : return "lv.all_ge_h"; |
---|
1281 | case morpheo::behavioural::INSTRUCTION_LV_ALL_GT_B : return "lv.all_gt_b"; |
---|
1282 | case morpheo::behavioural::INSTRUCTION_LV_ALL_GT_H : return "lv.all_gt_h"; |
---|
1283 | case morpheo::behavioural::INSTRUCTION_LV_ALL_LE_B : return "lv.all_le_b"; |
---|
1284 | case morpheo::behavioural::INSTRUCTION_LV_ALL_LE_H : return "lv.all_le_h"; |
---|
1285 | case morpheo::behavioural::INSTRUCTION_LV_ALL_LT_B : return "lv.all_lt_b"; |
---|
1286 | case morpheo::behavioural::INSTRUCTION_LV_ALL_LT_H : return "lv.all_lt_h"; |
---|
1287 | case morpheo::behavioural::INSTRUCTION_LV_ALL_NE_B : return "lv.all_ne_b"; |
---|
1288 | case morpheo::behavioural::INSTRUCTION_LV_ALL_NE_H : return "lv.all_ne_h"; |
---|
1289 | case morpheo::behavioural::INSTRUCTION_LV_AND : return "lv.and"; |
---|
1290 | case morpheo::behavioural::INSTRUCTION_LV_ANY_EQ_B : return "lv.any_eq_b"; |
---|
1291 | case morpheo::behavioural::INSTRUCTION_LV_ANY_EQ_H : return "lv.any_eq_h"; |
---|
1292 | case morpheo::behavioural::INSTRUCTION_LV_ANY_GE_B : return "lv.any_ge_b"; |
---|
1293 | case morpheo::behavioural::INSTRUCTION_LV_ANY_GE_H : return "lv.any_ge_h"; |
---|
1294 | case morpheo::behavioural::INSTRUCTION_LV_ANY_GT_B : return "lv.any_gt_b"; |
---|
1295 | case morpheo::behavioural::INSTRUCTION_LV_ANY_GT_H : return "lv.any_gt_h"; |
---|
1296 | case morpheo::behavioural::INSTRUCTION_LV_ANY_LE_B : return "lv.any_le_b"; |
---|
1297 | case morpheo::behavioural::INSTRUCTION_LV_ANY_LE_H : return "lv.any_le_h"; |
---|
1298 | case morpheo::behavioural::INSTRUCTION_LV_ANY_LT_B : return "lv.any_lt_b"; |
---|
1299 | case morpheo::behavioural::INSTRUCTION_LV_ANY_LT_H : return "lv.any_lt_h"; |
---|
1300 | case morpheo::behavioural::INSTRUCTION_LV_ANY_NE_B : return "lv.any_ne_b"; |
---|
1301 | case morpheo::behavioural::INSTRUCTION_LV_ANY_NE_H : return "lv.any_ne_h"; |
---|
1302 | case morpheo::behavioural::INSTRUCTION_LV_AVG_B : return "lv.avg_b"; |
---|
1303 | case morpheo::behavioural::INSTRUCTION_LV_AVG_H : return "lv.avg_h"; |
---|
1304 | case morpheo::behavioural::INSTRUCTION_LV_CMP_EQ_B : return "lv.cmp_eq_b"; |
---|
1305 | case morpheo::behavioural::INSTRUCTION_LV_CMP_EQ_H : return "lv.cmp_eq_h"; |
---|
1306 | case morpheo::behavioural::INSTRUCTION_LV_CMP_GE_B : return "lv.cmp_ge_b"; |
---|
1307 | case morpheo::behavioural::INSTRUCTION_LV_CMP_GE_H : return "lv.cmp_ge_h"; |
---|
1308 | case morpheo::behavioural::INSTRUCTION_LV_CMP_GT_B : return "lv.cmp_gt_b"; |
---|
1309 | case morpheo::behavioural::INSTRUCTION_LV_CMP_GT_H : return "lv.cmp_gt_h"; |
---|
1310 | case morpheo::behavioural::INSTRUCTION_LV_CMP_LE_B : return "lv.cmp_le_b"; |
---|
1311 | case morpheo::behavioural::INSTRUCTION_LV_CMP_LE_H : return "lv.cmp_le_h"; |
---|
1312 | case morpheo::behavioural::INSTRUCTION_LV_CMP_LT_B : return "lv.cmp_lt_b"; |
---|
1313 | case morpheo::behavioural::INSTRUCTION_LV_CMP_LT_H : return "lv.cmp_lt_h"; |
---|
1314 | case morpheo::behavioural::INSTRUCTION_LV_CMP_NE_B : return "lv.cmp_ne_b"; |
---|
1315 | case morpheo::behavioural::INSTRUCTION_LV_CMP_NE_H : return "lv.cmp_ne_h"; |
---|
1316 | case morpheo::behavioural::INSTRUCTION_LV_CUST1 : return "lv.cust1"; |
---|
1317 | case morpheo::behavioural::INSTRUCTION_LV_CUST2 : return "lv.cust2"; |
---|
1318 | case morpheo::behavioural::INSTRUCTION_LV_CUST3 : return "lv.cust3"; |
---|
1319 | case morpheo::behavioural::INSTRUCTION_LV_CUST4 : return "lv.cust4"; |
---|
1320 | case morpheo::behavioural::INSTRUCTION_LV_MADDS_H : return "lv.madds_h"; |
---|
1321 | case morpheo::behavioural::INSTRUCTION_LV_MAX_B : return "lv.max_b"; |
---|
1322 | case morpheo::behavioural::INSTRUCTION_LV_MAX_H : return "lv.max_h"; |
---|
1323 | case morpheo::behavioural::INSTRUCTION_LV_MERGE_B : return "lv.merge_b"; |
---|
1324 | case morpheo::behavioural::INSTRUCTION_LV_MERGE_H : return "lv.merge_h"; |
---|
1325 | case morpheo::behavioural::INSTRUCTION_LV_MIN_B : return "lv.min_b"; |
---|
1326 | case morpheo::behavioural::INSTRUCTION_LV_MIN_H : return "lv.min_h"; |
---|
1327 | case morpheo::behavioural::INSTRUCTION_LV_MSUBS_H : return "lv.msubs_h"; |
---|
1328 | case morpheo::behavioural::INSTRUCTION_LV_MULS_H : return "lv.muls_h"; |
---|
1329 | case morpheo::behavioural::INSTRUCTION_LV_NAND : return "lv.nand"; |
---|
1330 | case morpheo::behavioural::INSTRUCTION_LV_NOR : return "lv.nor"; |
---|
1331 | case morpheo::behavioural::INSTRUCTION_LV_OR : return "lv.or"; |
---|
1332 | case morpheo::behavioural::INSTRUCTION_LV_PACK_B : return "lv.pack_b"; |
---|
1333 | case morpheo::behavioural::INSTRUCTION_LV_PACK_H : return "lv.pack_h"; |
---|
1334 | case morpheo::behavioural::INSTRUCTION_LV_PACKS_B : return "lv.packs_b"; |
---|
1335 | case morpheo::behavioural::INSTRUCTION_LV_PACKS_H : return "lv.packs_h"; |
---|
1336 | case morpheo::behavioural::INSTRUCTION_LV_PACKUS_B : return "lv.packus_b"; |
---|
1337 | case morpheo::behavioural::INSTRUCTION_LV_PACKUS_H : return "lv.packus_h"; |
---|
1338 | case morpheo::behavioural::INSTRUCTION_LV_PERM_N : return "lv.perm_n"; |
---|
1339 | case morpheo::behavioural::INSTRUCTION_LV_RL_B : return "lv.rl_b"; |
---|
1340 | case morpheo::behavioural::INSTRUCTION_LV_RL_H : return "lv.rl_h"; |
---|
1341 | case morpheo::behavioural::INSTRUCTION_LV_SLL : return "lv.sll"; |
---|
1342 | case morpheo::behavioural::INSTRUCTION_LV_SLL_B : return "lv.sll_b"; |
---|
1343 | case morpheo::behavioural::INSTRUCTION_LV_SLL_H : return "lv.sll_h"; |
---|
1344 | case morpheo::behavioural::INSTRUCTION_LV_SRA_B : return "lv.sra_b"; |
---|
1345 | case morpheo::behavioural::INSTRUCTION_LV_SRA_H : return "lv.sra_h"; |
---|
1346 | case morpheo::behavioural::INSTRUCTION_LV_SRL : return "lv.srl"; |
---|
1347 | case morpheo::behavioural::INSTRUCTION_LV_SRL_B : return "lv.srl_b"; |
---|
1348 | case morpheo::behavioural::INSTRUCTION_LV_SRL_H : return "lv.srl_h"; |
---|
1349 | case morpheo::behavioural::INSTRUCTION_LV_SUB_B : return "lv.sub_b"; |
---|
1350 | case morpheo::behavioural::INSTRUCTION_LV_SUB_H : return "lv.sub_h"; |
---|
1351 | case morpheo::behavioural::INSTRUCTION_LV_SUBS_B : return "lv.subs_b"; |
---|
1352 | case morpheo::behavioural::INSTRUCTION_LV_SUBS_H : return "lv.subs_h"; |
---|
1353 | case morpheo::behavioural::INSTRUCTION_LV_SUBU_B : return "lv.subu_b"; |
---|
1354 | case morpheo::behavioural::INSTRUCTION_LV_SUBU_H : return "lv.subu_h"; |
---|
1355 | case morpheo::behavioural::INSTRUCTION_LV_SUBUS_B : return "lv.subus_b"; |
---|
1356 | case morpheo::behavioural::INSTRUCTION_LV_SUBUS_H : return "lv.subus_h"; |
---|
1357 | case morpheo::behavioural::INSTRUCTION_LV_UNPACK_B : return "lv.unpack_b"; |
---|
1358 | case morpheo::behavioural::INSTRUCTION_LV_UNPACK_H : return "lv.unpack_h"; |
---|
1359 | case morpheo::behavioural::INSTRUCTION_LV_XOR : return "lv.xor"; |
---|
1360 | |
---|
1361 | default : return ""; |
---|
1362 | } |
---|
1363 | }; |
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1364 | |
---|
1365 | }; // end namespace morpheo |
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1366 | |
---|
1367 | #endif |
---|